Bsi bs en 16603 50 14 2014

BS EN 16603-50-14:2014 BSI Standards Publication Space engineering — Spacecraft discrete interfaces BS EN 16603-50-14:2014 BRITISH STANDARD National foreword This British Standard is the UK implementation of EN 16603-50-14:2014 The UK participation in its preparation was entrusted to Technical Committee ACE/68, Space systems and operations A list of organizations represented on this committee can be obtained on request to its secretary This publication does not purport to include all the necessary provisions of a contract Users are responsible for its correct application © The British Standards Institution 2014 Published by BSI Standards Limited 2014 ISBN 978 580 84191 ICS 49.140 Compliance with a British Standard cannot confer immunity from legal obligations This British Standard was published under the authority of the Standards Policy and Strategy Committee on 30 September 2014 Amendments/corrigenda issued since publication Date Text affected EN 16603-50-14 EUROPEAN STANDARD NORME EUROPÉENNE EUROPÄISCHE NORM September 2014 ICS 49.140 English version Space engineering - Spacecraft discrete interfaces Ingénierie spatiale - Interfaces électriques discrètes pour satellites Raumfahrttechnik - Diskrete Schnittstellen in Raumfahrzeugen This European Standard was approved by CEN on March 2014 CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CEN and CENELEC member This European Standard exists in three official versions (English, French, German) A version in any other language made by translation under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels © 2014 CEN/CENELEC All rights of exploitation in any form and by any means reserved worldwide for CEN national Members and for CENELEC Members Ref No EN 16603-50-14:2014 E BS EN 16603-50-14:2014 EN 16603-50-14:2014 Table of contents Foreword Scope Normative references Terms, definitions and abbreviated terms 3.1 Terms from other standards 3.2 Terms specific to the present standard .9 3.3 Abbreviated terms 10 3.4 Conventions 11 3.4.1 Bit numbering convention 11 3.4.2 Timing diagram conventions 11 3.4.3 Signal and signal event naming convention 12 3.4.4 Signal timing and measurement references 13 General 14 4.1 Introduction .14 4.2 Architectural concepts 14 4.2.1 Overview 14 4.2.2 General failure tolerance 15 4.2.3 Interface control during power cycling 16 4.2.4 Cross-strapping 17 4.2.5 Harness cross-strapping 18 4.2.6 Cable capacitance 21 Analogue signal interfaces 22 5.1 Overview 22 5.2 Analogue signal monitor (ASM) interface 22 5.3 5.2.1 General .22 5.2.2 Analogue signal monitor interface 24 Temperature sensors monitor (TSM) interface 26 5.3.1 Overview 26 5.3.2 TSM acquisition layout 27 5.3.3 TSM acquisition resolution 27 5.3.4 TSM wire configuration 27 BS EN 16603-50-14:2014 EN 16603-50-14:2014 5.3.5 TSM electrical characteristics 28 Bi-level discrete input interfaces 36 6.1 6.2 Bi-level discrete monitor (BDM) interface 36 6.1.1 Overview 36 6.1.2 Bi-level discrete monitor interface 36 Bi-level switch monitor (BSM) interface 38 6.2.1 General principles .38 6.2.2 Bi-level switch monitor interface 39 Pulsed command interfaces 41 7.1 7.2 High power command (HPC) interfaces 41 7.1.1 General principles .41 7.1.2 High power command interface 41 7.1.3 Low voltage high power command (LV-HPC) electrical characteristics 42 7.1.4 High voltage high power command (HV-HPC) electrical characteristics 44 7.1.5 High current high power command (HC-HPC) electrical characteristics 45 7.1.6 Wiring type 46 7.1.7 High power command interface arrangement 46 Low power command (LPC) interface 47 7.2.1 General .47 7.2.2 Low power command interface 47 7.2.3 LPC electrical characteristics 48 7.2.4 Wiring type 49 7.2.5 Interface arrangement .49 Serial digital interfaces 50 8.1 Foreword 50 8.2 General principles of serial digital interfaces 50 8.3 8.4 8.2.1 Overview 50 8.2.2 General requirements 51 16-bit input serial digital (ISD) interface 52 8.3.1 16-bit input serial digital interface description 52 8.3.2 Signals skew .52 8.3.3 ISD interface timing specification 52 8.3.4 16-bit input serial digital interface: signal description 55 16-bit output serial digital (OSD) interface description 57 8.4.1 16-bit output serial digital interface description 57 BS EN 16603-50-14:2014 EN 16603-50-14:2014 8.4.2 Signals skew .57 8.4.3 OSD interface timing specification 58 8.4.4 16-bit output serial digital interface signal description 59 8.5 16-bit bi-directional serial digital (BSD) interface description 61 8.6 Serial digital interface electrical circuits description 62 8.7 Balanced differential serial digital interface signals 63 8.8 8.7.1 Balanced differential serial digital interface - GATE_WRITE circuits 63 8.7.2 Balanced differential serial digital interface - DATA_CLK_OUT circuits 63 8.7.3 Balanced differential serial digital interface - DATA_OUT circuits 63 8.7.4 Balanced differential serial digital interface - DATA_IN circuits 64 8.7.5 Balanced differential serial digital interface - GATE_READ circuits 64 Serial digital interface circuit electrical characteristics 64 8.8.1 Introduction .64 8.8.2 Provisions 64 Annex A (informative) Tailoring guidelines 68 Bibliography 69 Figures Figure 3-1: Bit numbering convention 11 Figure 3-2: Timing diagram conventions .12 Figure 3-3: Signal timing and measurement references 13 Figure 4-1: Architectural context of interfaces defined in this standard 15 Figure 4-2: General scheme of redundant unit’s cross-strapping 17 Figure 4-3: Example scheme for Single source – Dual receiver cross-strapping 19 Figure 4-4: Example scheme for Dual source – Single receiver cross-strapping 20 Figure 4-5: Cable capacitance definitions .21 Figure 5-1: Analogue signal monitor (single ended source) interface arrangement 26 Figure 5-2: Analogue signal monitor (differential source) interface arrangement 26 Figure 5-3: TSM1 reference model .29 Figure 5-4: Requirement for ∆Rth/Rth as a function of RNORM and Rth ∆x = ±0,01 29 Figure 5-5: TSM1 interface arrangement 31 Figure 5-6: TSM2 interface arrangement 33 Figure 5-7: Example TSM1 and 4K3A354 thermistor 34 Figure 5-8: Example TSM1 and YSI44907 thermistor 34 Figure 5-9: Example TSM2 and PT1000 thermistor 35 Figure 6-1: BDM Interface configuration 38 BS EN 16603-50-14:2014 EN 16603-50-14:2014 Figure 6-2: Switch status circuit interface arrangement 40 Figure 7-1: HPC interface arrangement 46 Figure 7-2: LPC active signal output voltage vs load current 48 Figure 7-3: LPC-P and LPC-S interface arrangement 49 Figure 8-1: 16-bit input serial digital (ISD) interface signal arrangement 52 Figure 8-2: 16-bit input serial digital (ISD) interface 53 Figure 8-3: 16-bit output serial digital (OSD) interface signal arrangement 57 Figure 8-4: 16-bit output serial digital (OSD) interface 58 Figure 8-5: 16-bit bi-directional serial digital interface signal arrangement 62 Figure 8-6: Balanced differential circuits for serial digital interfaces 63 Figure 8-7: Example of serial digital interface arrangement 65 Figure 8-8: Threshold levels for ECSS-E-50-14 differential circuits 67 Tables Table 5-1: Analogue signal monitor source circuit characteristics 24 Table 5-2 Analogue signal receiver circuit characteristics 25 Table 5-3: TSM1 source circuit characteristics 29 Table 5-4: TSM1 receiver circuit characteristics 30 Table 5-5: TSM2 source characteristics .32 Table 5-6: TSM2 receiver characteristics .32 Table 6-1: BDM source characteristics 37 Table 6-2: BDM receiver characteristics .37 Table 6-3: Switch source characteristics 39 Table 6-4: Switch receiver characteristics 40 Table 7-1: LV-HPC source characteristics 43 Table 7-2: LV-HPC receiver characteristics 43 Table 7-3: HV-HPC source characteristics 44 Table 7-4: HV-HPC receiver characteristics 45 Table 7-5: HC-HPC source characteristics 45 Table 7-6: HC-HPC receiver characteristics 46 Table 7-7: LPC source characteristics 48 Table 7-8: LPC receiver characteristics 49 Table 8-1: 16-bit input serial digital (ISD) interface characteristics 54 Table 8-2: tb values .56 Table 8-3: 16-bit output serial digital (OSD) interface characteristics 59 Table 8-4: Serial digital interface electrical characteristics 66 BS EN 16603-50-14:2014 EN 16603-50-14:2014 Foreword This document (EN 16603-50-14:2014) has been prepared by Technical Committee CEN/CLC/TC “Space”, the secretariat of which is held by DIN This standard (EN 16603-50-14:2014) originates from ECSS-E-ST-50-14C This European Standard shall be given the status of a national standard, either by publication of an identical text or by endorsement, at the latest by March 2015, and conflicting national standards shall be withdrawn at the latest by March 2015 Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights CEN [and/or CENELEC] shall not be held responsible for identifying any or all such patent rights This document has been prepared under a mandate given to CEN by the European Commission and the European Free Trade Association This document has been developed to cover specifically space systems and has therefore precedence over any EN covering the same scope but with a wider domain of applicability (e.g : aerospace) According to the CEN-CENELEC Internal Regulations, the national standards organizations of the following countries are bound to implement this European Standard: Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom BS EN 16603-50-14:2014 EN 16603-50-14:2014 Scope This standard specifies a common set of spacecraft onboard electrical interfaces for sensor acquisition and actuator control The interfaces specified in this standard are the traditional point-to-point interfaces that are commonly used on modern spacecraft The interfaces specified in this standard include analogue and discrete digital interfaces used for status measurement and control, as well as point-to-point serial digital interfaces used for digital data acquisition and commanding of devices This standard specifies: • interface signal identification; • interface signal waveforms; • signal timing requirements; • signal modulation; • voltage levels; • input and output impedance; • overvoltage protection requirements; • bit ordering in digital data words; • cabling requirements where appropriate This standard does not cover: • connector requirements; • digital data word semantics; • message or block formats and semantics Connector requirements are not covered because these are normally mission or project specific The goal of this standard is to establish a single set of definitions for these interfaces and to promote generic implementations that can be re-used throughout different missions When referred, the present standard is applicable as a complement of the already existing interface standards ANSI/TIA/EIA-422B-1994 and ITU-T Recommendation V.11 (Previously “CCITT Recommendation”) – (03/93) Guidance for tailoring of the present standard can be found in Annex A This Standard may be tailored for the specific characteristics and constraints of a space project in conformance with ECSS-S-ST-00 BS EN 16603-50-14:2014 EN 16603-50-14:2014 Normative references The following normative documents contain provisions which, through reference in this text, constitute provisions of this ECSS Standard For dated references, subsequent amendments to, or revisions of any of these publications, not apply However, parties to agreements based on this ECSS Standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below For undated references the latest edition of the publication referred to applies EN reference Reference in text Title EN 16601-00-01 ECSS-S-ST-00-01 ECSS system - Glossary of terms ANSI/TIA/EIA-422B-1994 Electrical characteristics of balanced voltage digital interface circuits ITU-T Recommendation V.11 (Previously “CCITT Recommendation”) – (03/93) Electrical characteristics for balanced doublecurrent interchange circuits operating at data signalling rates up to 10 Mbit/s NOTE This document is technically ANSI/TIA/EIA/422B-1994 equivalent to BS EN 16603-50-14:2014 EN 16603-50-14:2014 8.4.2.2 Provisions a Maximum skew measured at core side shall be ∆t = 0,02 × tb b Maximum skew measured at peripheral side shall be ∆t = 0,04 × tb 8.4.3 OSD interface timing specification The timing diagram shown in Figure 8-4 and the timing parameters in Table 8-3 specify the timing of the operational requirements specified in 8.4.4 for the 16bit output serial digital interface A data transfer is started by the core element asserting the GATE_WRITE signal to indicate that a data transfer is underway After this (tb0) the core element places the value of the most significant data bit (bit 0) on the DATA_OUT line Some time after the GATE_WRITEDOWN, 16 low going pulses are output on the DATA_CLK_OUT signal Each bit of the data word, including bit-0 is guaranteed valid on the DATA_CLK_OUT falling edge and for a given period before, data set up time tsu, and after it, data hold time tdh GATE_WRITE is de-asserted after the last GATE_CLK_OUTDOWN This deassertion can thus occur before the final GATE_CLK_OUTUP GATE_WRITE then is not reasserted before the interface recovery period has expired ts trec GATE_WRITE tcd tb8 tch tb tgd DATA_CLK_OUT DATA_OUT 16 tdv tdh tb0 10 11 12 13 14 15 Figure 8-4: 16-bit output serial digital (OSD) interface BS EN 16603-50-14:2014 EN 16603-50-14:2014 Table 8-3: 16-bit output serial digital (OSD) interface characteristics Reference Parameter Description Maximum Minimum 8.4.1 a.1 tb Bit sampling interval tb (MAX) tb (MIN) 8.4.1 a.2 ts Repeated transfer period a ∞ tb × 17 8.4.1 a.3 tb0 Bit data valid after GATE_WRITEDOWN tb/4 - 8.4.1 a.4 tcd Clock delay, GATE_WRITEDOWN to first DATA_CLK_OUTDOWN tb × + ∆t tb/2 – ∆t 8.4.1 a.5 tdh Data hold after DATA_CLK_OUTDOWN - tb/8 – ∆t 8.4.1 a.6 tsu Data valid before DATA_CLK_OUTDOWN - tb/4 – ∆t Time DATA_CLK_OUT high (clock duty cycle) measured at core element tb/2 × 1,1 tb/2 × 0,9 Time DATA_CLK_OUT high (clock duty cycle) measured at peripheral element tb/2 × 1,2 tb/2 × 0,8 8.4.1 a.7.(a) tch 8.4.1 a.7.(b) 8.4.1 a.8 tgd Gating delay, last DATA_CLK_OUTDOWN to GATE_WRITEUP tb × + ∆t tb/2 – ∆t 8.4.1 a.9 trec Recovery interval, GATE_WRITEUP to GATE_WRITEDOWN ∞ tb – ∆t 8.4.1 a.10 tb8 Extension of gap b between clock pulse and tb × a The transfer period is calculated as follows: ts = tcd + tgd + trec + 15·tb b This is to allow 8-bit bursts in TTC-B-01 fashion 8.4.4 16-bit output serial digital interface signal description 8.4.4.1 16-bit output serial digital - signals a The 16-bit output serial digital interface shall consist of three signals named GATE_WRITE, DATA_CLK_OUT, and DATA_OUT b Signals shall be differential 8.4.4.2 a 16-bit output serial digital - GATE_WRITE signal The core element shall provide a GATE_WRITE signal asserted by the core element during a data transfer operation BS EN 16603-50-14:2014 EN 16603-50-14:2014 8.4.4.3 a 16-bit output serial digital - GATE_WRITE signal quiescent state During quiescence, i.e when no data transfer is taking place, the GATE_WRITE signal shall be maintained at a high logic level by the core element 8.4.4.4 16-bit output serial digital - DATA_CLK_OUT signal a The core element shall provide a DATA_CLK_OUT signal b The DATA_CLK_OUT signal shall comprise sixteen low going pulses during each data transfer operation c The DATA_CLK_OUT burst shall last 16 times the bit sampling pseudoperiod (tb) plus the optional extension of the clock gap between clock pulses and (tb8) 8.4.4.5 a 16-bit output serial digital - DATA_CLK_OUT signal quiescent state Peripheral elements shall ignore the DATA_CLK_OUT signal when the GATE_WRITE signal is not asserted NOTE 8.4.4.6 a 16-bit output serial digital - DATA_OUT signal The core element shall provide a DATA_OUT signal used to transfer the data word bit serially 8.4.4.7 a The reason is that during quiescence, i.e when no data transfer is taking place, the DATA_CLK_OUT signal can oscillate (e.g if it is shared with other peripheral elements) 16-bit output serial digital - DATA_OUT signal quiescent state Peripheral elements shall ignore the DATA_OUT signal when the GATE_WRITE signal is not asserted NOTE 8.4.4.8 The reason is that during quiescence, i.e when no data transfer is taking place, the DATA_OUT signal can change (e.g if it is shared with other peripheral elements) 16-bit output serial digital - data transfer a Data transfer on the 16-bit OSD shall be started by the core element, asserting the GATE_WRITE signal b Shortly after the GATE_WRITEDOWN the core element shall set the DATA_OUT signal to the value of the most significant bit, bit 0, of the data word to be transferred BS EN 16603-50-14:2014 EN 16603-50-14:2014 c The core element shall ensure that the DATA_OUT signal is valid on each falling edge of the DATA_CLK_OUT (DATA_CLK_OUTDOWN) when GATE_WRITE is asserted d The DATA_OUT signal shall meet the data set-up and hold times as specified in Table 8-3 e Shortly after (after tdh) each DATA_CLK_OUT falling edge (DATA_CLK_OUTDOWN), the core element shall update the value of the DATA_OUT signal to the value of the next most significant bit NOTE f When the 8th clock pulse on DATA_CLK_OUT has been generated, the gap to the next clock pulse may be increased by up to tb × g When bit 15 of DATA_IN is reached, any value may be used; NOTE 8.4.4.9 a a The reason is that the next value of DATA_OUT is not important since the peripheral element does not sample the DATA_OUT signal after this 16-bit output serial digital - bit sampling interval, tb The bit sampling interval, tb, i.e the interval between successive DATA_CLK_OUT rising edges, should be selected from the options shown in Table 8-2 8.4.4.10 16-bit output serial digital - sampling period, ts The sampling period, ts, defined as the minimum period between one GATE_WRITEDOWN and the next opportunity for a GATE_WRITEDOWN, shall be not less than tb × 17 NOTE 8.5 That means that if the current value of DATA_OUT is bit n, the new value of DATA_OUT is bit n+1 The transfer period is calculated as follows: ts = tcd + tgd + trec + 15∙tb 16-bit bi-directional serial digital (BSD) interface description The 16-bit bi-directional serial digital interface provides a bi-directional serial digital data transfer capability using five signals as shown in Figure 8-5: • GATE_WRITE, • GATE_READ, • DATA_CLK_OUT, • DATA_OUT, and • DATA_IN The GATE_WRITE and GATE_READ signals are used to indicate the direction of the transfer The signal timing during output transfers is identical to that for the 16-bit output serial digital interface and during input transfers it is identical to the 16-bit input serial digital interface BS EN 16603-50-14:2014 EN 16603-50-14:2014 CORE PERIPHERAL GATE_WRITE (OSD) GATE_READ (ISD) DATA_CLK_OUT (OSD + ISD) DATA_OUT (OSD) DATA_IN (ISD) Figure 8-5: 16-bit bi-directional serial digital interface signal arrangement There are two advantages offered by this interface • Firstly, it offers the possibility of writing a data value out to a peripheral element and then reading the same value back in order to verify that the write operation was performed correctly • Secondly, the interface can be expanded to address more than one register location within a peripheral element using only two extra signals for each additional register The extra signals used are a dedicated GATE_WRITE(READ) signal for each new register to be accessed All of the other signals can be common to all registers This means that n registers can be accessed using only 2n + signals which can lead to significant savings in terms of cables and connectors During an input transfer the data is input via the DATA_IN signal and the DATA_OUT signal assumes its quiescence state During a data output transfer the data is output on the DATA_OUT signal and the DATA_IN signal assumes its quiescence state 8.6 Serial digital interface electrical circuits description The serial digital interface circuits are the conducting paths which convey the data and control signals which make up the interface between the core and peripheral elements Each circuit consists of the conductors and any connectors or other components which comprise the electrical path Two circuits are used for each signal These circuits operate in a balanced mode with reference to the core element differential ground potential, i.e when one circuit carries a positive voltage, the complementary circuit carries a negative voltage of the same magnitude Figure 8-6 shows the relationship between circuits, signals, and the interface definition point for balanced differential serial digital interfaces BS EN 16603-50-14:2014 EN 16603-50-14:2014 Point of Interface Definition +ve Output Signal Core Element VOH I OH -ve Output Circuits I OL I OL VOL Local Connection Points Input Circuits +ve Input Signal I OH VIH I I -ve VIL IH Peripheral Element IH I IL I IL * * *Reference potential for balanced voltage measurements Figure 8-6: Balanced differential circuits for serial digital interfaces 8.7 Balanced differential serial digital interface signals 8.7.1 Balanced differential serial digital interface GATE_WRITE circuits a A balanced differential pair of circuits called GATE_WRITE+ and GATE_WRITE- shall be provided b The balanced differential pair specified in 8.7.1a shall be driven by the core element, and carry the GATE_WRITE signal 8.7.2 Balanced differential serial digital interface DATA_CLK_OUT circuits a A balanced differential pair of circuits called DATA_CLK_OUT+ and DATA_CLK_OUT- shall be provided b The balanced differential pair specified in 8.7.2a shall be driven by the core element, and carry the DATA_CLK_OUT signal 8.7.3 a Balanced differential serial digital interface DATA_OUT circuits For output serial digital interfaces, a balanced differential pair of circuits called DATA_OUT+ and DATA_OUT- shall be provided BS EN 16603-50-14:2014 EN 16603-50-14:2014 b The balanced differential pair specified in 8.7.3a shall be driven by the peripheral element, and carry the DATA_OUT signal 8.7.4 a For input serial digital interfaces, a balanced differential pair of circuits called DATA_IN+ and DATA_IN- shall be provided b The balanced differential pair specified in 8.7.4a shall be driven by the peripheral element, and carry the DATA_IN signal 8.7.5 8.8 Balanced differential serial digital interface DATA_IN circuits Balanced differential serial digital interface GATE_READ circuits a For bi-directional serial digital interfaces, a balanced differential pair of circuits called GATE_READ+ and GATE_READ- shall be provided b The balanced differential pair specified in 8.7.5a shall be driven by the core element, and carry the GATE_READ signal Serial digital interface circuit electrical characteristics 8.8.1 Introduction ANSI/TIA/EIA-422 (hereafter briefly RS-422) defines a balanced (differential) interface; specifying a single, unidirectional driver with multiple receivers (up to 32) RS-422 will support Point-to-Point, Multi-Drop circuits, but not MultiPoint Although the EIA standard does not show circuit grounding in either of the RS422 circuits, this Standard includes recommendation on grounding in 8.8.2a 8.8.2 a Provisions Serial digital interface circuits should be grounded as follows: The drivers and receivers should be connected directly to circuit ground The circuit ground should be connected to chassis ground NOTE Cabling is not specified in RS-422 but information can be found in [V11] NOTE Figure 8-7 illustrates this provision BS EN 16603-50-14:2014 EN 16603-50-14:2014 b Serial digital interface circuit electrical characteristics shall meet the requirements specified in Table 8-4 NOTE Table 8-4 includes characteristics for compatibility with RS-422 (indicated with the number (422) in the table), and specific characteristics NOTE The values specified here-in grant operations in the following conditions: correct • maximum signal frequency: MHz; • maximum cable length: 16 m; • cable type: Twisted Shielded Pair 120 Ω Impedance NOTE Compliance to the parameters indicated by the note (422) in Table 8-4 can be achieved by use of the following circuits: HS-26C(T)31RH HS-26C(T)32RH HS-26CLV31RH HS-26CLV32RH Items and are V supplied devices, items and are 3,3 V supplied devices These devices can interoperate and comply with the specification in Table 8-4 c Serial digital interface shall be compliant to the interface arrangement specified in Figure 8-7 d Compliance to microcircuits characteristics others than the parameters indicated by the note (422) in Table 8-4., shall be verified on the project by Review of Design or Test Figure 8-7: Example of serial digital interface arrangement BS EN 16603-50-14:2014 EN 16603-50-14:2014 Table 8-4: Serial digital interface electrical characteristics Reference Characteristics Value Type Notes SOURCE CIRCUIT 8.8 a.1 Electrical characteristics Differential (422) 8.8 a.2 Differential output voltage open circuit, VOC 1,8 V ≤ |VOC| ≤ 6,0 V Specific 8.8 a.3 Output voltage TRUE and Ve ≤ V COMP lines, Ve (422) 8.8 a.4 Differential output impedance, Zout 105 Ω ≤ Zout ≤ 135 Ω Specific 8.8 a.5 Short circuit output current, IA |IA| ≤ 150 mA for each terminal to ground (422) 8.8 a.6 Rise time, tr tr ≤ 0,1 × tb if tb ≥ 200 ns tr ≤ 20 ns if tb ≤ 200 ns (422) Note 8.8 a.7 Output leakage current in power off, IO |IO| ≤ 100 µA (422) Note 8.8 a.8 Fault voltage emission, Vsfe V to V (through 50 Ω minimum series resistance) Specific 8.8 a.9 Fault voltage tolerance, Vsft -1,5 V to V (applied through kΩ series resistance Ris) Specific Note RECEIVER CIRCUIT 8.8 a.10 Electrical characteristics Differential (422) 8.8 a.11 Series protection, Ris * kΩ Specific 8.8 a.12 Max input voltage (each input w.r.t ground), VI ± 10 V (422) Note 8.8 a.13 Common mode – V to + V acceptance (V1+V2)/2, VCM Specific Note 8.8 a.14 Differential input voltage, VDI ± |600 mV to V| each voltage in this range must be interpreted as valid signal Specific Note 8.8 a.15 Fault voltage emission, Vrfe V to 5,5 V (through kΩ series resistance Ris) Specific 8.8 a.16 Fault voltage tolerance, Vrft -1,5 V to 8,5 V Specific Note 1: Output impedance to be matched with 120 Ω cable impedance Recommended range of the Ros resistors between 50 Ω and 60 Ω, considering 10 Ω typical driver output impedance, when using HS26C(T)31RH Note 2: tb time duration of the unit interval at the applicable data rate (normally 0,5 * period duration) Note 3: –0,25 V to +6 V applied at the output terminals Note 4: RS-422 standard parameters given for reference only Note 5: This figure is compatible with both performances of V and 3,3 V devices (HS26CLV32RH) Note 6: Minimum threshold considering kΩ series resistors (the devices commonly used have a threshold of ±400 mV, for reference see Figure 8-8) BS EN 16603-50-14:2014 EN 16603-50-14:2014 Figure 8-8: Threshold levels for ECSS-E-50-14 differential circuits BS EN 16603-50-14:2014 EN 16603-50-14:2014 Annex A (informative) Tailoring guidelines Tailoring for this Standard is limited to the adoption of specific discrete interfaces listed hereby: • • • • Analogue signal interfaces  Analogue signal monitor (ASM) interface  Temperature sensors monitor (TSM) interfaces Bi-level discrete input interfaces  Bi-level discrete monitor (BDM) interface  Bi-level switch monitor (BSM) interface Pulsed command interfaces  High power command (HPC) interfaces  Low power command (LPC) interface Serial digital interfaces  16-bit input serial digital (ISD) interface  16-bit output serial digital (OSD) interface description  16-bit bi-directional serial digital (BSD) interface description Modification of existing or addition of requirements within a specific interface definition should not be done BS EN 16603-50-14:2014 EN 16603-50-14:2014 Bibliography EN reference Reference in text Title EN 16601-00 ECSS-S-ST-00 ECSS system - Description, implementation and general requirements EN 16603-50-14:2014 This page deliberately left blank This page deliberately left blank NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAW British Standards Institution (BSI) BSI is the national body responsible for preparing British Standards and other standards-related publications, information and services BSI is incorporated by Royal Charter British Standards and other standardization products are published by BSI Standards Limited About us Revisions We bring together business, industry, government, consumers, innovators and others to shape their combined experience and expertise into standards -based solutions Our British Standards and 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