Introduction Parallel Computer Architectures Thoai Nam Khoa Khoa học và Kỹ thuật Máy tính – ĐH Bách Khoa TP HCM Outline Flynn’s Taxonomy Classification of Parallel Computers Based on Architectures[.]
Parallel Computer Architectures Thoai Nam Outline Flynn’s Taxonomy Classification of Parallel Computers Based on Architectures Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM Flynn’s Taxonomy Based on notions of instruction and data streams – – – – SISD (a Single Instruction stream, a Single Data stream ) SIMD (Single Instruction stream, Multiple Data streams ) MISD (Multiple Instruction streams, a Single Data stream) MIMD (Multiple Instruction streams, Multiple Data stream) Popularity – MIMD > SIMD > MISD Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM SISD SISD – Conventional sequential machines IS : Instruction Stream CU : Control Unit MU : Memory Unit DS : Data Stream PU : Processing Unit IS I/O CU IS PU DS MU Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM SIMD SIMD – Vector computers, processor arrays – Special purpose computations PE : Processing Element PE1 IS CU Program loaded from host DS LM : Local Memory LM1 DS IS PEn DS LMn DS Data sets loaded from host SIMD architecture with distributed memory Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM MISD MISD – Systolic arrays – Special purpose computations IS IS Memory (Program, Data) DS CU1 IS PU1 CU2 DS IS PU2 CUn IS DS PUn I/O MISD architecture (the systolic array) Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM DS MIMD MIMD – General purpose parallel computers IS IS DS CU1 PU1 I/O I/O CUn IS PUn DS Shared Memory IS MIMD architecture with shared memory Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM Classification based on Architecture Pipelined Computers Dataflow Architectures Data Parallel Systems Multiprocessors Multicomputers Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM Pipeline Computers (1) Instructions are divided into a number of steps (segments, stages) At the same time, several instructions can be loaded in the machine and be executed in different steps Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM Pipeline Computers (2) – – – – – IF – instruction fetch ID – instruction decode and register fetch EX- execution and effective address calculation MEM – memory access WB- write back Instruction # Instruction i IF ID EX IF ID EX IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM Instruction i+1 Instruction i+2 Instruction i+3 Instruction i+4 Cycles MEM WB MEM WB Khoa Khoa học Kỹ thuật Máy tính – ĐH Bách Khoa TP.HCM WB