Giáo trình Verilog HDL - Tác giả Samir Palnitkar

Kiến thức cơ bản về Verilog HDL ngôn ngữ lập trình Verilog HDL Thiết kế vi mạch bằng Verilog-HDL Verilog HDL Programming

Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996 PART 1 BASIC VERILOG TOPICS 1 Overview of Digital Design with Verilog HDL 2 Hierarchical Modeling Concepts 3 Basic Concepts 4 Modules and Ports 5 Gate-Level Modeling 6 Dataflow Modeling 7 Behavioral Modeling 8 Tasks and Functions 9 Useful Modeling Techniques PART 2 Advance Verilog Topics 10 Timing and Delays 11 Switch- Level Modeling 12 User-Defined Primitives 13 Programming Language Interface 14 Logic Synthesis with Verilog HDL PART3 APPENDICES A Strength Modeling and Advanced Net Definitions B List of PLI Rountines C List of Keywords, System Tasks, and Compiler Directives D Formal Syntax Definition E Verilog Tidbits F Verilog Examples 1 3 11 27 47 61 85 115 157 169 191 193 213 229 249 275 319 321 327 343 345 363 367 .. .Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996 PART BASIC VERILOG TOPICS Overview of Digital Design with Verilog HDL Hierarchical Modeling... Gate-Level Modeling Dataflow Modeling Behavioral Modeling Tasks and Functions Useful Modeling Techniques PART Advance Verilog Topics 10 Timing and Delays 11 Switch- Level Modeling 12 User-Defined... with Verilog HDL PART3 APPENDICES A Strength Modeling and Advanced Net Definitions B List of PLI Rountines C List of Keywords, System Tasks, and Compiler Directives D Formal Syntax Definition E Verilog