uClinux on the NetFPGA Embedded System Stanford High-Performance Networking Group

uClinux on the NetFPGA Embedded System Stanford High-Performance Networking Group Justin Erickson Acknowledgements I would like to thank the Stanford High-Performance Networking Group for providing me the opportunity to work on this project and for all their support throughout the project I would especially like to thank Greg Watson and Paul Hartke for guiding me through all the difficulties Table of Contents Introduction History of the NetFPGA Project 2.1 Project Motivation .7 2.2 NetFPGA v1 Design 2.3 Problems with NetFPGA v1 Overview of the NetFPGA Platform 3.1 Hardware Overview 3.2 Software Overview 11 3.3 Solutions to NetFPGA problems .12 Software Implementation 13 4.1 Overview of Challenges 13 4.2 Overview of Build Process 14 4.2.1 Building the Base System 14 4.2.2 Building uClinux .15 4.2.3 Uploading the Configuration to the Board 16 4.3 Building on the Common XUPV2P Board 16 4.4 Building on NetFPGA Board 18 Test Software 20 5.1 Overview 20 5.2 Building the Test Application 20 5.3 Results 21 Conclusion .22 6.1 Current Status 22 6.2 Lessons Learned 22 6.3 Future .23 Appendix: NetFPGA with uClinux Design Tutorial 25 General Requirements 25 Installing the Software Tools .25 Creating the Hardware from Xilinx Platform Studio (XPS) .26 Building uClinux 30 Uploading the Hardware and uClinux to the NetFPGA Board 31 Adding Custom User Applications to uClinux 33 Finding Help 33 References 34 Introduction This thesis will detail my role in the Stanford High-Performance Networking group working on the NetFPGA project NetFPGA is a customizable software and hardware solution aimed at allowing students to create network hardware that most accurately simulates real-world network hardware I am specifically working on the secondgeneration NetFPGA board The overall idea is to develop a platform that provides computer science and electrical engineering students full control to develop both the software and hardware for a network device The NetFPGA board combines memory, a processor, and a FPGA (Field Programmable Array) on a standard PCI board, which will easily be integrated into standard PCs today The FPGA chip is a Xilinx technology which can dynamically alter itself to implement user-customized hardware, while the memory and processor enable software to run on the board as well The FPGA chip has enough logic components to run a processor within it rather than the embedded processor, which is what we decided to in this project for reasons to be further discussed in Section The NetFPGA project is a group within the Stanford High-Performance Networking group and funded by the National Science Foundation About ten people are currently working on the project, and it has been in development since about 2004 I joined the project fall of 2006 and have been working on porting the operating system and software toolchain necessary to enable students to easily develop and deploy their software solutions on the NetFPGA board As I will detail in Section 4, we decided to port the uClinux operating system, which is a variant of Linux specifically catered to small embedded systems due to the NetFPGA’s memory constraints and the user community’s knowledge of Linux After getting the toolchain up and running, I developed test software as a proof of concept that the NETFPGA project was a viable platform for developing networking devices and to ensure that the necessary software toolchain and libraries were configured properly To provide context for my discussion of my part of the project, this thesis provide background in Sections and Section will specifically provide a brief description of the whole NetFPGA project It will start with the overall motivations and design for the first NetFPGA project and finish with the results and problems that second-generation NetFPGA board aims to correct Section will provide an architectural overview of the new NetFGPA design and how we will overcome the issues encountered in the original NetFPGA design Section will also introduce the software architecture that was the focus of my work Sections and will detail my specific contribution to the NetFPGA project and the challenges I encountered in getting the necessary software toolchain in place Section will describe porting uClinux to the NetFPGA hardware platform using the Xilinx and Microblaze toolchain Section will detail the test software I designed to demonstrate the viability of NetFPGA as practical and realistic development platform for networking devices Section will discuss the current status of the NetFPGA project as well as lessons learned and the future of NetFPGA The Appendix will contain a tutorial on how to create a working uClinux system for the NetFPGA board As explained in Section 4, it is far easier to reference a base configuration for a similar design than to create an entirely new configuration because the Xilinx tools are designed for full flexibility and as such not prevent non-working configurations For more information on porting uClinux to platforms similar to NetFPGA, Jason Wu from the University of Queensland, Australia has a great tutorial located at http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf [1] History of the NetFPGA Project 2.1 Project Motivation The overarching goal of the NetFPGA project is to provide students with a practical and realistic way to learn, develop, and create networking devices such as routers and switches Prior to the NetFPGA project, the only practical way to implement networking devices or algorithms cost-effectively and quickly was through software While software implementations allow students to understand how networking algorithms and protocols work, it does not provide an accurate representation of real-world networking implementations because the long-term trend has been towards designing customized hardware for faster implementations of networking algorithms Another problem with software implementations is that they are inherently slower than customized hardware solutions Thus, to provide more effective simulation of networking solutions, the NetFPGA project aims to create an inexpensive and practical networking platform that allows users to develop customized hardware 2.2 NetFPGA v1 Design The original NetFPGA board contains three Field Programmable Arrays (FPGAs), which are chips that accept a Hardware Description Language such as Verilog and dynamically alter themselves to implement the described hardware logic Two of these FPGAs are available for the user to customize for their individual hardware solution, while the third is used to control the interaction between the user’s hardware and the Ethernet controller Each FPGA has its own SRAM memory bank The NetFPGA board also has an Ethernet controller with eight Ethernet 10 Mb/s ports The Ethernet ports serve the obvious purpose of allowing users to design multi-port switches, routers, etc…, as well as providing a means of receiving the new FPGA descriptions from a NetFPGA server using a customized protocol designed to control the FPGA Figure shows a visualization of the overall architecture [2] Figure 1: Architectural Overview of the NetFPGA Board [2] 2.3 Problems with NetFPGA v1 While NetFPGA succeeded in its original goal of providing a cost- and time-effective environment to test and run customized network hardware, it has some fundamental shortcomings that prevent it from achieving widespread use outside the Stanford community The largest drawback of NetFPGA v1 is the difficulty in setting up and configuring a new cluster of NetFPGA boards The NetFPGA boards required a custom rack and special networking switches [2] Another issue is that the boards cannot run software While the trend in industry is towards hardware implementations of networking solutions, many industry networking devices implement the more advanced functionality in software in an embedded system Overview of the NetFPGA Platform 3.1 Hardware Overview In general, the design of the new NetFPGA board is similar to the original NetFPGA board It, however, has an embedded processor as well as the capability to run a processor within one of its FPGAs, thus enabling software to run in addition to the custom hardware While the board can run as a self-sustained unit, it is built to run in a standard full-sized PCI slot on a host box The PCI connection allows the host machine to interact with the NetFPGA board for configuration and debugging Instead of three FPGAs, the new NetFPGA board uses two FPGAs, a larger Vertex2Pro and a smaller Spartan-II The Spartan-II is programmed to handle the PCI bus communications and exposes a simpler interface to the Virtex2Pro chip, which handles the board’s networking capabilities and run the user-defined hardware (see Figure 2) [3] Figure 2: Block diagram of NetFPGA’s two FPGAs The red circle is where the user design runs [3] The NetFPGA board contains four gigabit Ethernet ports, 4MB of SRAM, and a PowerPC processor The inclusion of the SRAM bank and processor enable the board to run user-designed software as well as hardware Furthermore, the Vertex2Pro is large enough to store and run Xilinx’s softcore Microblaze processor, which is a simple processor designed to run inside an FPGA As the PCI protocol does not change, there will seldom be a need to change the SpartanII configuration, so it will automatically load the PCI protocol implementation from a Flash chip at startup From the user’s perspective, managing the specific implementation details of the memory controller, PCI interface, and multiple MAC arbiter is generally uninteresting and superfluous to the design, so the default NetFPGA configuration gives the user a simplified abstraction of the actual hardware by providing a virtual LAN layer Therefore, the user design interacts with the virtual LAN layer, PCI interface exposed by the Spartan-II, and the SRAM controller The PCI interface will also be used to push the user FPGA design into the system and provide advanced debugging capabilities Since the user design will change frequently, it will not be stored statically on the board but rather downloaded to the FPGA whenever necessary Figure shows the simplified user view of the NetFPGA board 10 Test Software 5.1 Overview The final part of my project was to create a software application to run on uClinux which will verify that the interaction between the hardware and software is properly in place and to ensure that the user has everything necessary to develop functional network devices While it would have been desirable to have developed a fully working router, the complexities of integrating uClinux with the hardware design required more attention than originally anticipated Instead, I decided to test all the base components necessary to build a router, such as the ability to send and receive packets The main objectives of the test application are to ensure that the software can properly configure the hardware to route packets and that the hardware correctly sends and receives packets to and from the software The testing proved useful as it uncovered hardware issues that were obstacles to developing a router 5.2 Building the Test Application The lack of a memory management unit in the uClinux operating system was beneficial to building a user application that interacts with the hardware because the flat file system exposes all memory, including the memory-mapped-device registers, to user applications This enabled me to easily create a user application which can read and write directly from the hardware registers Following the UNET-CPU-ROUTER4 specification, I created an application to test the necessary components required to build a network device such as a router [5] First, I created tests to verify that the software can configure the hardware to act as a router by creating a test application that allows the user to configure the IP and MAC addresses of all four Ethernet ports, the IP routing table, and the ARP table for mapping 20 IP to MAC addresses of connected nodes Through the test application I was able to configure the hardware to operate as a simple router In addition to testing the hardware’s capability to route, I added tests to verify that the hardware properly transferred packets to the software when necessary and that the software was able to send packets over the network This effectively tests the basic components that are necessary for the proper functioning of the software as part of the network device 5.3 Results The tests proved that a user application on uClinux could successfully and easily interact with the hardware in a simple and effective manner; they also uncovered underlying problems in the hardware that we are currently working to resolve in order to enable full routing functionality While the test application could successfully configure the IP routing table, ARP table, IP addresses, and MAC addresses as well as send packets, it showed that the hardware has problems routing packets and sending packets that are sent from software After a few adjustments to the hardware and replacing a faulty board, the tests successfully executed, confirming that all the tools are in place to build a router The software could properly configure the hardware to route packets as desired and could send and receive packets when necessary Based on these results, I am confident that a user could develop a fully functioning router using the current toolchain 21 Conclusion 6.1 Current Status Currently, NetFPGA is the only system specifically designed for designing customized network hardware in academia As discussed in Section 2, however, the non-intuitive setup process and custom-sized boards have limited its adoption outside Stanford University At Stanford, the NetFPGA boards are the primary development resource for CS344, Projects in Computer Networks It has proven itself as a viable and useful resource for teaching students how to develop realistic hardware routers The Stanford High-Performance Networking group, however, is hoping to address the problems of original NetFPGA with new NetFPGA board to enable widespread adoption at tertiary institutions such as those Section Currently, the second-generation NetFPGA board is still in development but is on track for its debut in Stanford’s CS344 class next winter Even though we have been specifically focusing your efforts on designing a network device development platform, we are aware of some interest from outside researches, who were attracted to the design and cost-effectiveness of the second version of the NetFPGA system Since the new NetFPGA is not currently available for outside use, the precise amount of third-party interest is unknown 6.2 Lessons Learned Overall, working on the NetFPGA project has proved to be a valuable experience in learning about hardware interacts with software in basic computers and in porting operating systems to new hardware configurations In addition to the domain knowledge I have gained, I have learned a few general practices that I feel will be applicable to future endeavors The main thing I learned was how difficult it is to attack a completely new problem without experience in a known similar problem Specifically, I found it difficult 22 identify what was going wrong when first designing the hardware for the XUPV2P system without Xilinx’s working reference project Once I started reverse engineering the reference project to determine what was missing from my new configuration, getting uClinux running was significantly easier Moreover, due to the investment in designing hardware with the XUPV2P board, designing hardware specific for the NetFPGA board was rather uncomplicated As for the NetFPGA project itself, the main thing we learned from the software side is the how limiting 4MB of memory is While cost-effectiveness is extremely important, the ceiling of 4MB of SRAM proved to be far more limiting than originally anticipated and may prove to be a limiting factor in the design of complicated user applications on the NetFPGA board 6.3 Future The new NetFPGA project is on track for use in CS344 next year, when it should prove to be an effective teaching tool for designing routers and other network hardware The standard full-sized PCI form factor, ease of setup, and cost efficiency will hopefully attract interest in the academic community outside of Stanford It is hard, however, to estimate ahead of time how many academic institutions will adopt the NetFPGA platform As previously mentioned, there is some known interest from the research community in utilizing the NetFPGA board for their own projects, but because the second-generation NetFPGA board is still in development, it is hard to judge the number of researchers So far, NetFPGA seems to be poised to be the sole embedded system for developing realistic network applications in academia and seems to have sparked interest from the outside community even during development Thus, the Stanford High-Performance Networking Group has decided to open-source license the project to enable this growing community to help sustain future develop on the system and allow users complete flexibility in how to cater the system to their individual demands 23 In addition to the community development efforts, the Stanford High-Performance Networking Group will also start designing the next version of the NetFPGA board to solve the issues that have arisen in working with the NetFPGA board such as the limited memory resources 24 Appendix: NetFPGA with uClinux Design Tutorial This appendix will provide a step-by-step tutorial on how to create the hardware and software necessary to run uClinux on a NetFPGA board As much of this tutorial is based on Jason Wu’s tutorial, it might be helpful to reference it as well It is freely available on the web at: http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf [1] General Requirements NetFPGA board Xilinx ISE and EDK software Linux machine NetFPGA Board Support Package (BSP) uClinux BSP Microblaze Toolchain uClinux Distribution NetFPGA SRAM pcores Installing the Software Tools You will need at least one machine that runs Linux I will assume that the NetFPGA board has already been installed and setup correctly, and for the most part I’ll assume that all the necessary software installations are available The rest of this section will explain how to install all the necessary tools listed above in the general requirements section The next section will begin the tutorial on how to configure the uClinux hardware 25 First, you need to install Xilinx ISE and EDK The only special note here is that you should install ISE before the EDK This does not have to be the same machine you are building uClinux on or the same machine as the physical NetFPGA board Install the uClinux BSP which is on John William’s site: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/platforms.html on the same machine as the Xilinx tools [5] Simply extract these files either to the EDK installation’s parent directory under the subdirectory edk_user_repository (e.g., if the EDK is located at C:\EDK then extract the BSP to C:\EDK\edk_user_repository) or your own custom folder If you extract to your own custom folder, you will need to specify this later to the Xilinx tools Extract the NetFPGA BSP files just as above Note you can also put these in a separate folder than the uClinux BSP, but once again you will need to specify this customized folder later That is all that is necessary for building the hardware platform from Xilinx Now you need to configure the tools to actually build uClinux for the hardware The steps to installing the Microblaze toolchain and configuring the uClinux distribution are exactly as explained in Jason Wu’s tutorial: http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf [1] So rather then repeat them here, please follow the directions on pages through 11 of the tutorial Creating the Hardware from Xilinx Platform Studio (XPS) Now that everything is installed, you are ready to create the necessary hardware in using XPS and Base System Builder (BSB) Once again this will be based on Jason Wu’s tutorial with some modifications to work for the NetFPGA board instead of the Vertex ML401 Evaluation Platform [1] Follow the following steps to build the hardware using XPS: 26 Start XPS Select Base System Builder Wizard and press OK Enter the path to store the XPS project If the uClinux or NetFPGA BSP is in a custom directory (i.e., a directory other than the edk_user_repository in EDK’s parent directly), then check User Repository search path for IP, driver, and library files and enter the paths to the BSP directories separated by a semi-colon Select I would like to create a new design and press OK Select Stanford as Board Vender The rest of the options will fill in automatically, so press Next Select Microblaze as the processor and press Next Ensure the Processor-Bus Clock Frequency is 62.5MHz, On-chip H/W debug module selected, and No Cache is selected Then press Next Ensure RS232 Uart is selected and select Use Interrupt for it Deselect LEDs 4Bit and press Next 10 Deselect DIPSWs 4Bit and PushButtons 5Bit before pressing Next 11 Press the Add Peripheral… button and add an OPB TIMER 12 Ensure the Counter Bit Width is 32 Select One timer is present and Use Interrupt, then press Next 13 There may be a warning dialog that the system does not have output ports This can safely be ignored, so press OK 14 Make sure STDIN and STDOUT are both set to RS232_UART_1 The sample applications are completely optional Press Next 15 Keep the rest of the options and press Next, Generate, or OK 16 Select Start Using Platform Studio and OK on the dialog 17 Select Project | Add/Edit Cores… 18 Under the Ports tab add an Interrupt for the debug_module 19 In the Internal Ports Connections scroll box find opb_interc_0 and press the … button under the Net Name column 27 20 Add debug_module_Interrupt to the Interrupts Connected There should now be the following three things in Interrupts Connected: opb_timer_1_Interrupt, RS232_Uart_1_Interrupt, and debug_module_Interrupt Press OK 21 Press OK again in the Add/Edit Hardware Platform Specifications dialog 22 Now select Project | Software Platform Settings… 23 On the Software Platform tab, under the Kernel and Operating Systems box, select uclinux as the OS 24 In the Processor, Driver Parameters and Interrupt Handlers set the CORE_CLOCK_FREQUENCY to 62500000 25 Go to the Library/OS Parameters tab 26 Set both stdout and stdin to RS232_Uart_1 27 Set main_memory_bank to 28 Set main_memory_start to 0x7a000000 29 Set main_memory_size to 0x00400000 30 Set lmb_memory to ilmb_cntlr 31 Press OK to get out of the Software Platform Settings 32 On the left of the main XPS window select the Applications tab Right click on Default: microblaze_0_bootloop and select Mark to Initialize BRAMs 33 Make sure that no other project is marked to initialize BRAMs Now you need to add the SRAM banks to the uClinux design First you need to modify the system.mhs file in the main project directory Add the following lines before the begin statements (you may want to copy this from another NetFPGA project): PORT sram1_addr = sram1_addr, VEC = [18:0], DIR = O PORT sram1_data = sram1_data, VEC = [35:0], DIR = IO PORT sram1_we_bw = sram1_we_bw, DIR = O PORT sram2_addr = sram2_addr, VEC = [18:0], DIR = O PORT sram2_data = sram2_data, VEC = [35:0], DIR = IO PORT sram2_we_bw = sram2_we_bw, DIR = O BEGIN nf2_sramc 28 PARAMETER INSTANCE = nf2_sramc_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x7b000000 PARAMETER C_HIGHADDR = 0x7b00ffff PARAMETER C_AR0_BASEADDR = 0x7a000000 PARAMETER C_AR0_HIGHADDR = 0x7a1fffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT Mem_A = sram1_addr PORT Mem_DQ = sram1_data PORT Mem_WEN = sram1_we_bw END BEGIN nf2_sramc PARAMETER INSTANCE = nf2_sramc_1 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x7b100000 PARAMETER C_HIGHADDR = 0x7b10ffff PARAMETER C_AR0_BASEADDR = 0x7a200000 PARAMETER C_AR0_HIGHADDR = 0x7a3fffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT Mem_A = sram2_addr PORT Mem_DQ = sram2_data PORT Mem_WEN = sram2_we_bw END You need to add the SRAM information to the data/system.ucf Because there are many of lines to add here, I will assume that a copy is available from another project 29 You also need to add the SRAM IP cores a pcores subdirectory of the main project directory Finally, to actually build the project: Select Tools | Generate Libraries and BSP Select Tools | Generate Bitstream This should take a while to finish Building uClinux Before building uClinux, you need to copy and modify the configuration file from your XPS project to uClinux You need to switch the Uartlite and MDM addresses and IRQs in order to get uClinux to output to the debug window: Copy microblaze_0/libsrc/uclinux_v1_00_d/auto-config.in in the subdirectory of the main project folder to linux-2.4.x/arch/microblaze/platform/uclinux-auto subdirectory of the uClinux repository If you are copying from Windows to Linux you need to convert the line endings by opening it in vi, then running typing “:set ff=unix”, and then saving and exiting Open the auto-config.in file in an editor Scroll down to the Definitions for MDM_0 and Definitions for UARTLITE_0 Swap the BASEADDR, HIGHADDR, and IRQ values for the two Save and exit the file Now you are ready to build uClinux, so from the main directory of the uClinux repository, the following: Run make real_clean to ensure you removed any previous build settings Run make menuconfig so you can configure the uClinux configurations Select Vender/Product Selection Select Xilinx as the Vender you wish to target 30 Select uclinux-auto as the Product you with to target Select Exit to exit out of this window Select Kernel/Library/Defaults Selection Under this submenu, enable both Customize Kernel Settings and Customize Vender/User Settings Select Exit twice to exit completely 10 When prompted, press to select all the default options, except when prompted about Flash size select none 11 When the menu comes up under Processor type and features, deselect GPIO driver, Ethernet driver, and Debug logging 12 Under General setup deselect Networking support 13 Under Kernel hacking deselect Full Symbolic/Source Debugging support 14 Select Exit to exit the menu and then select Save 15 On the next menu, deselect every application under Network Applications 16 Select Exit to exit the menu and then select Save 17 Run make dep 18 Run make all Uploading the Hardware and uClinux to the NetFPGA Board Before you can upload, you need a computer with the Xilinx ISE and EDK installed and connect to the NetFPGA board via JTAG On this computer, the following: Create a new project directory Copy the hardware binary from the XPS project under implementation/download.bit to this directory Copy the uClinux image from images/image.bin subdirectory of the uClinux repository to this directory Get the marvell.bsd file for the Ethernet interfaces Create an xmd.ini file in this directory and copy the following as one line: 31 connect mb mdm -configdevice devicenr idcode 0x0061c093 irlength partname XCV200 -configdevice devicenr idcode 0x0127e093 irlength 14 partname XC2VP30 -configdevice devicenr idcode 0x0 irlength partname phy -debugdevice deviceNr cpunr Now add the following as individual lines: # jtag_uart_server perhaps only works with EDK 8.1?? # terminal -jtag_uart_server terminal dow -data image.bin 0x7a000000 mwr 0x100 rwr 0x100 rwr pc 0x7a000000 Open Xilinx Impact Press Cancel if a dialog box comes up to load or create a project Select File | Initialize Chain 10 Press OK to error messages that come up You can safely ignore these messages as you are about to program the chips 11 Press Cancel on the first TWO Assign New Configuration File dialog boxes 12 Press Yes on the Unknown Device File Query dialog box 13 Select the marvell.bsd file and then press Open 14 Right click on the middle (xc2vp30) chip in the main Impact window and select Assign New Configuration File 15 Select the download.bit you just copied over and press Open then OK 16 Right click on the middle chip again and press Program… 17 Make sure Verify is not checked in the dialog that pops up and press OK 18 Run xmd.exe in the directory with both image.bin and xmd.ini 19 uClinux should boot up 20 The default username and password is root and root 32 Adding Custom User Applications to uClinux In the main folder of the uClinux repository, there is a tutorial that outlines exactly how to add your own applications to uClinux located at: Documentation/Adding-User-Apps-HOWTO Finding Help As uClinux and much of the NetFPGA software is open source or proprietary there is dedicated support, but I found that help can be found with a bit of work The resources that I found useful are:  Web search engines, especially Google Groups, are a great first resource for seeing if other people have solutions to similar problems  John William’s site (http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/) proved to be another invaluable resource [5]  The Microblaze mailing list, which you can subscribe to from John William’s site, is the best way to get answers from the community [5]  Another resource which is sometimes helpful is the newsgroup, comp.arch.fpga but this is for the FPGA hardware architecture not uClinux or Microblaze 33 References [1] J Wu and J Williams, The University of Queensland Australia, “Microblaze uClinux: Creating a Simple uClinux ready Microblaze Design,” August 15, 2005, http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf [2] H Fu (hwfu@stanford.edu), and H H Ng (harnhua@stanford.edu), Stanford HighPerformance Networking Group, Stanford University, “NetFPGA – Hardware Design Platform for Network Applications: Documentation for Developing User Modules,” June 6, 2002, http://klamath.stanford.edu/NetFPGA/docs/user_doc.pdf [3] G Watson (gwatson@stanford.edu), Stanford High-Performance Networking Group, Stanford University, “NF2 Overview,” May 19, 2006, http://klamath.stanford.edu/nf2/docs/overview.pdf [4] Xilinx, “Getting Started with EDK,” February 15, 2005, http://www.xilinx.com/ise/embedded/edk7_1docs/edk_getstarted.pdf [5] Stanford High-Performance Networking Group, UNET-CPU-ROUTER4, Stanford University, April 20, 2006 [6] J Williams, The University of Queensland Australia, “Microblaze uClinux Home Page,” May 12, 2006, http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ [7] Stanford High-Performance Networking Group, Stanford University, “NF2 (NetFPGA 2.0),” May 2006, http://klamath.stanford.edu/nf2/ 34 ... of the toolset to the new NetFPGA environment, I worked on porting the XUPV2P configuration to the NetFPGA board 13 As mentioned in the Section 3, a major limitation of the NetFPGA board is the. .. Overview Unlike the original NetFPGA, the second-generation NetFPGA is designed to allow software to run on the board on the embedded processor Despite these improvements, the new NetFPGA board... project for reasons to be further discussed in Section The NetFPGA project is a group within the Stanford High-Performance Networking group and funded by the National Science Foundation About ten