Advanced Operating Systems - Lecture 28: Page fault frequency (PFF). This lecture will cover the following: fault resumption lets us lie about many things; emulate reference bits; emulate non-existent instructions; run OS on top of another OS; P6 memory system;...
CS703 Advanced Operating Systems By Mr Farhan Zaidi Lecture No. 28 Page Fault Frequency (PFF) PFF is a variable-space algorithm that uses a more ad hoc approach Attempt to equalize the fault rate among all processes, and to have a “tolerable” system-wide fault rate monitor the fault rate for each process if fault rate is above a given threshold, give it more memory so that it faults less if the fault rate is below threshold, take away memory should fault more, allowing someone else to fault less Fault resumption. lets us lie about many things Emulate reference bits: Emulate non-existent instructions: Set page permissions to “invalid” On any access will get a fault: Mark as referenced Give inst an illegal opcode When executed will cause “illegal instruction” fault Handler checks opcode: if for fake inst, do, otherwise kill Run OS on top of another OS! linux Make OS into normal process When it does something “privileged” the real OS will get woken up with a fault linux win98 linux privileged 32 bit address space P6 Memory System KB page size L1, L2, and TLBs 4-way set associative DRAM external system bus (e.g PCI) inst TLB 32 entries L2 cache data TLB 64 entries cache bus bus interface unit instruction fetch unit processor package L1 i-cache sets inst TLB data TLB L1 d-cache 16 sets L1 i-cache and d-cache 16 KB 32 B line size 128 sets L2 cache unified 128 KB MB P6 2level Page Table Structure Page directory Up to 1024 page tables 1024 4-byte page directory entries (PDEs) that point to page tables 1024 PTEs Page tables: 1024 4-byte page table entries (PTEs) that point to pages page directory 1024 PDEs 1024 PTEs 1024 PTEs Translating with the P6 TLB CPU 20 VPN 12 virtual address VPO Partition VPN into TLBT and TLBI Is the PTE for VPN cached in set TLBI? 16 TLBT TLBI TLB miss PDE page table translation TLB PTE hit 20 PPN 12 PPO physical address Yes: then build physical address No: then read PTE (and PDE if not cached) from memory and build physical address ... d-cache 16 sets L1 i-cache and d-cache 16 KB 32 B line size 128 sets L2 cache unified 128 KB MB P6 2level Page Table Structure Page directory Up to 1024 page tables 1024 4-byte.. .Lecture? ?No. 28 Page Fault Frequency (PFF) PFF is a variable-space algorithm that uses a more ad hoc approach Attempt to equalize... 4-way set associative DRAM external system bus (e.g PCI) inst TLB 32 entries L2 cache data TLB 64 entries cache bus bus interface unit instruction fetch unit processor package L1 i-cache