High Gain High Efficiency Doherty Amplifiers with Optimized Driver Stages44890

ponent However, the analysis points out that the PAE-6dB difference between the two approaches depends on GDPA, ηD, and β Let’s assume the DPA output stage efficiency ηDPA = 45%, driver gain is 10 dB, and β = 0.9 (the values are deducted from simulations of a single stage Doherty amplifier at 10 GHz using a 0.15-μm enhancement mode GaAs process) Fig illustrates the overall PAE at 6-dB PBO as a function of driver efficiency at three different gain levels The overall PAE is reduced when either the driver efficiency or the output stage gain drops Moreover, when the output stage has high gain, the driver efficiency has minimal effect on the overall PAE, thus, the performance is strongly determined by the output Doherty stage gain and PAE As a result, if the output stage’s gain is large enough, the difference in PAE between the two approaches is very minimal (only around 1%) Therefore, the single driver topology can be preferably deployed due to its simplicity and compactness On the contrary, when the gain of the output stage is lower than 10 dB, the difference between the two topologies can be noticeable In this case, the dual driver topology should be used to avoid significant efficiency degradation III DPA DESIGN AND VERIFICATION (a) (a) (b) Fig Measured small signal performance of (a) the 10 GHz single driver DPA, and (b) the 28 GHz dual driver DPA (b) Fig (a) Single driver 10 GHz DPA and (b) Dual driver 28 GHz DPA (photo size is not for scale) To verify the concept, two Doherty amplifiers at 10 GHz and 28 GHz are fabricated in a 0.15-μm GaAs process The chip photos of two DPAs are shown in Fig The first DPA at 10 GHz employs a single driver while the 28 GHz DPA utilizes the dual driver topology The two different topologies are chosen for the two DPAs since the 10 GHz output stage can offer much higher gain than the 28 GHz output stage does By employing the single driver topology, the total chip size of the 10 GHz DPA is smaller, which is only 3.3 mm x 1.2 mm (0.0044λ2) as compared to 2.9 mm x 1.7 mm (0.043λ2) of the 28 GHz DPA (note that the 10 GHz DPA is much smaller in terms of wavelength) Furthermore, single driver topology requires only three gate bias voltages while still maintains high overall PAE at 6-dB PBO On the other hand, because the transistors have limited gain at Ka-band, the dual driver topology must be used in the 28 GHz DPA to minimize the effect of the driver’s PAE on the overall PAE It is also worth noting that the 28 GHz DPA employs stacked-FET cells at the output stage to improve the output power [12], and the two DPAs can achieve similar power levels (a) (b) Fig Measured output power versus gain and power added efficiency of (a) the 10 GHz single driver DPA, and (b) the 28 GHz dual driver DPA TABLE I BIAS CONDITION OF THE TWO PROPOSED DPAS Output stage Driver stage Topology Vd2 Vg2 Vd1 Vg1 Main 4V 0.35 V 10 GHz Single 4V 0.4 V driver DPA Peaking 4V 0.12 V Main 8V 0.4 V 4V 0.45 V 28 GHz Dual driver DPA Peaking 8V 0.05 V 4V 0.05 V Fig presents the measured small signals of the two DPAs at the bias condition depicted in Table I The 10 GHz single driver DPA achieves 19.2 dB gain at 10 GHz and the 3-dB bandwidth covers from 8.75 to 11 GHz The 28 GHz has a measured gain of 14.3 dB at 28 GHz and maintains higher than 11 dB from 25.5 to 29.5 GHz According to simulation, the 422 output stage of the 28 GHz DPA can only provide 6.5 dB gain while the output stage of the 10 GHz DPA can achieve up to 11 dB gain Therefore, based on our proposed analysis, the single driver approach is only suitable for the 10 GHz amplifier Fig presents the measured PAE and gain of the DPAs at 10 GHz and 28 GHz, respectively The single driver DPA achieves a peak PAE of 43% at 26.8 dBm output power and 32.5% PAE at 6-dB power back-off In this design, the driver transistor is carefully chosen so that the driver stage starts to have soft compression at the power level equivalent to around 3-dB power back-off of the DPA As a result, the driver can still maintain high efficiency at 6-dB PBO at the cost of heavier DPA gain compression From Fig 6(a), the DPA reaches its peak PAE at 3.5 dB gain compression According to Fig 6(b), in the 28 GHz DPA, the peak PAE of 37% is measured at 28.2 dBm output power which is also the 1-dB gain compression point Utilizing the dual driver topology, the DPA exhibits a PAE of 27% at 6-dB PBO without scarifying the power gain flatness Fig presents the measured adjacent channel power ratio (ACPR) of the two prototypes Without digital pre-distortion (DPD), the 28 GHz dual driver DPA exhibits better linearity than the single driver DPA since the dual driver has much less gain compression However, with DPD, the ACPR of the 10 GHz DPA is lower and reaches almost -50 dBc This can be explained by the fact that the DPD loop works much more efficient at 10 GHz as compared to 28 GHz IV CONCLUSION In this paper, detailed analysis and numerical comparison between two major approaches in implementing driver stages for DPAs have been demonstrated When the output stage has reasonable gain, a single driver is preferred since it reduces the chip size and complexity with only a small reduction in PAE On the other hand, when the output stage provides low gain, the dual driver topology is required to prevent significant PAE drop Two DPA prototypes at 10 GHz and 28 GHz are fabricated and measured to verify the proposed concept To the best of the authors’ knowledge, both fabricated prototypes achieve the highest gain when compared to other reported DPAs at similar frequency ranges TABLE II COMPARISON TO OTHER HIGH-FREQUENCY DPAS Freq (GHz) Power (dBm) Gain (dB) PAEpeak (%) This work 10 9.5 9.56 10 36 29 39 27 Psat 9.2 7.2 19 47 37 38.5 43 31 33.5 29 32 8.74 7.74 92.4 (†) 3.96 [6] 24 30.9 Psat 12.5 38 20 4.29 [7] 28.5 26 Psat 12 40 29 2.86 23 36.8 Psat 15 48 Ref [2] [3] [4]* [8]* This work 28 28.2 P1dB 15 37 (*) GaN technology; (†) Matching networks on PCB PAE6-dB Chip size (mm2) PBO (%) 25 6.8 27 4.93 REFERENCES [1] D P Nguyen, B L Pham, and A Pham, "A Compact Ka-Band Integrated Doherty Amplifier With Reconfigurable Input Network," IEEE Trans Microw Theory Techn., vol 67, no 1, pp 205-215, 2019 [2] M Coffey, P MomenRoodaki, A Zai, and Z Popovic, "A 4.2-W 10GHz GaN MMIC Doherty Power Amplifier," in Proc IEEE Compound Semiconductor Integr Circuit Symp (CSICS), 2015, pp 1-4 [3] P Colantonio et al., "Increasing Doherty Amplifier Average Efficiency Exploiting Device Knee Voltage Behavior," IEEE Trans Microw Theory Techn., vol 59, no 9, pp 2295-2305, 2011 [4] S Y Lee et al., "Linear X-band GaN HEMT transformer-based Doherty power amplifier," Electronics Lett., vol 52, no 15, pp 1342-1343, 2016 [5] A N Stameroff et al., "Wide-Bandwidth Power-Combining and Inverse Class-F GaN Power Amplifier at X-Band," IEEE Trans Microw Theory Techn., vol 61, no 3, pp 1291-1300, 2013 [6] R Quaglia, V Camarchia, T Jiang, M Pirola, S D Guerrieri, and B Loran, "K-Band GaAs MMIC Doherty Power Amplifier for Microwave Radio With Optimized Driver," IEEE Trans Microw Theory Techn., vol 62, no 11, pp 2518-2525, 2014 [7] D P Nguyen et al., "A compact 29% PAE at dB power back-off Emode GaAs pHEMT MMIC Doherty power amplifier at Ka-band," in IEEE MTT-S Int Microw Symp Dig., 2017, pp 1683-1686 [8] C F Campbell et al., “A K-band W Doherty amplifier MMIC utilizing 0.15 μm GaN on SiC HEMT technology,” in Proc IEEE Compound Semiconductor Integr Circuit Symp (CSICS), Oct 2012, pp 1–4 [9] D P Nguyen, J Curtis, and A V Pham, "A Doherty Amplifier With Modified Load Modulation Scheme Based on Load-pull Data," IEEE Trans Microw Theory Techn., vol 66, no 1, pp 227-236, 2018 [10] D P Nguyen, T Pham, and A Pham, "A 28-GHz Symmetrical Doherty Power Amplifier Using Stacked-FET Cells," IEEE Trans Microw Theory Techn., vol 66, no 6, pp 2628-2637, 2018 [11] A Keerti et al., "RF Characterization of SiGe HBT Power Amplifiers Under Load Mismatch," IEEE Trans Microw Theory Techn., vol 55, no 2, pp 207-214, 2007 [12] D P Nguyen et al., "A Ka-band asymmetrical stacked-FET MMIC Doherty power amplifier," in IEEE Radio Freq Integr Circuits Symp (RFIC), 2017, pp 398-401 (a) (b) Figure 7: Measured ACPR with and without digital pre-distortion (DPD) of the: (a) 10 GHz single driver DPA and (b) 28 GHz dual driver DPA Table II summarizes the performance of the two prototypes and compares with other state-of-the-art DPAs reported at similar frequencies Using optimized drivers for each design, our PAs achieve the highest gain while still maintaining high PAE at 6-dB PBO 423 ... single driver DPA, and (b) the 28 GHz dual driver DPA (b) Fig (a) Single driver 10 GHz DPA and (b) Dual driver 28 GHz DPA (photo size is not for scale) To verify the concept, two Doherty amplifiers. .. prototypes Without digital pre-distortion (DPD), the 28 GHz dual driver DPA exhibits better linearity than the single driver DPA since the dual driver has much less gain compression However, with DPD,... power versus gain and power added efficiency of (a) the 10 GHz single driver DPA, and (b) the 28 GHz dual driver DPA TABLE I BIAS CONDITION OF THE TWO PROPOSED DPAS Output stage Driver stage