Elimination of surface leakage in gate c

APPLIED PHYSICS LETTERS 99, 183503 (2011) Elimination of surface leakage in gate controlled type-II InAs/GaSb mid-infrared photodetectors G Chen, B.-M Nguyen, A M Hoang, E K Huang, S R Darvish, and M Razeghia) Department of Electrical Engineering and Computer Science, Center for Quantum Devices, Northwestern University, Evanston, Illinois 60208, USA (Received 26 September 2011; accepted 18 October 2011; published online November 2011) The electrical performance of mid-infrared type-II superlattice M-barrier photodetectors is shown to be limited by surface leakage By applying gate bias on the mesa sidewall surface, leakage current is significantly reduced Qualitatively IV modeling shows diffusion-dominated behavior of dark current at temperatures greater than 120 K At 110 K, the dark current of gated device is reduced by more than orders of magnitude, reaching the measurement system noise floor With a quantum efficiency of 48% in front side illumination configuration, a 4.7lm cut-off gated device attains a specific detectivity of 2.5  1014 cmHz1/2/W at 110 K, which is 3.6 times higher than in C 2011 American Institute of Physics [doi:10.1063/1.3658627] ungated devices V Type II InAs/GaSb superlattice (T2SL), proposed by Sai-Halasz et al.1 in the 1970s, has shown great progress in infrared detection2 from mid-wavelength infrared (MWIR) to very-long-wavelength infrared (VLWIR) regimes With significant improvement of material quality and device design, T2SL p-p-M-n heterostructure has achieved very high electrical bulk performance.3 Mesa-isolated detectors become strongly sensitive to devices’ sidewall quality because surface roughness or residual byproducts cause strong surface leakage Not only does surface leakage deteriorate device performance and hamper the uniformity of detector arrays but also overwhelms important bulk dark current mechanisms Evaluation of bulk performance and extraction of material parameters become challenging Revealing and suppressing surface leakage is among the biggest concerns for T2SL-mesa-isolated infrared detectors To suppress the surface leakage and investigate the bulk electrical performance, different surface treatments were attempted.4–7 However, they were mostly applied for wavelengths beyond MWIR regime because surface leakage was considered to be a minor factor in MWIR T2SL devices Therefore, recent work on MWIR focused on improving the bulk performance.8,9 In this work, we show that in MWIR T2SL M-barrier-based detectors, surface leakage still strongly affects their performance below 150 K By controlling the surface potential and band bending at device sidewalls, we can efficiently suppress the surface leakage and achieve higher detectivity This type of control enables more meaningful current-voltage (I-V) modeling to reveal dominant dark current mechanisms The origin of surface leakage is believed from abrupt termination of the periodic crystal structure, which creates a band bending on the mesa-sidewalls This band bending causes electron accumulation or type inversion at sidewall surfaces, resulting in a conduction channel along sidewalls.10 A dielectric passivation layer alters the band bending by its native fixed charges which can either improve or deteriorate the device performance In this work, we actively control the a) Electronic mail: razeghi@eecs.northwestern.edu 0003-6951/2011/99(18)/183503/3/$30.00 band bending by applying a voltage along device’s sidewall This concept11 is similar to metal-insulator-semiconductor (MIS) technology in field transistors Figure 1(a) shows the schematic diagram of the device while Figure 1(b) represents the effect of gate bias on the band bending at the insulator/ T2SL interface Without applying gate bias, band bending occurs and electrons are accumulated on the insulator/T2SL interface, which generates a conducting channel and causes surface leakage When applying negative gate bias, negative charges are stored at the metal-insulator interface and repel accumulated electrons away from the insulator/T2SL interface Therefore, flat band conditions can be established which suppresses surface leakage To investigate the effect of gating technique on surface leakage, a MWIR T2SL p-p-M-n heterojunction3 was grown on a GaSb substrate with molecular beam epitaxy On top of a 1.5 lm n-doped InAsSb buffer, the device structure consisted of a 0.5 lm thick n-contact (n $ 1018 cmÀ3), 0.5 lm thick lightly n-doped M-barrier,12 lm thick lightly p-doped (p $ 1017 cmÀ3) primary absorbing region, and 0.5 lm thick p-contact (p $ 1018 cmÀ3) and capped with a 20 nm thick ptype InAs capping layer The superlattice design for the absorbing and p-contact region used 7.5 monolayers (MLs) of InAs and 10 MLs of GaSb in one period and both were FIG (Color online) (a) Schematic diagram of a gated diode (b) Surface band diagram of gated diode at zero and negative gate bias 99, 183503-1 C 2011 American Institute of Physics V Downloaded 02 Nov 2011 to 129.105.215.146 Redistribution subject to AIP license or copyright; see http://apl.aip.org/about/rights_and_permissions 183503-2 Chen et al Appl Phys Lett 99, 183503 (2011) TABLE I The 50% power responsivity cut-off wavelengths, QE at peak responsivity under zero operation bias, and peak detectivity (D*) of UPD, UGD, and GD at saturation bias Temperature (K) k50% (lm) QE at peak responsivity (%) D*(Jones) Bias to maximize D* (mV) GD UGD UPD 110 120 130 140 150 180 4.68 48.4 2.5  1014 7.0  1013 5.8  1013 50 4.72 49.2 4.4  1013 2.2  1013 1.8  1013 50 4.77 50.2 7.5  1012 5.9  1012 5.2  1012 50 4.81 51.3 2.2  1012 1.9  1012 1.8  1012 50 4.83 52.2 8.9  1011 7.9  1011 7.6  1011 80 4.96 53.3 1.1  1011 9.6  1010 9.2  1010 100 doped with beryllium The M-barrier and n-contact consisted of 10/1/5/1 MLs of InAs/GaSb/AlSb/GaSb in one period The material was processed into two dies of single element diodes with diameters from 100 to 400 lm by standard processing techniques.13 One die (sample A) was unpassivated and used as reference for electrical and optical characterization The other die (sample B) was passivated with 0.6 lm thick SiO2 dielectric layer using ion beam deposition technology An additional metal gate was deposited on mesa sidewalls of half of diodes in sample B so that the sample contained both gated diodes (GDs) and ungated diodes (UGDs) In the final step, the top contacts were opened using electron cyclotron resonance etching The samples were wire-bonded onto 68 pin leadless ceramic chip carriers and loaded into cryostat for temperature dependent characterization Unpassivated diodes (UPDs) from sample A were characterized at temperatures from 110 K to 180 K The 50% responsivity cut-off wavelengths and quantum efficiency (QE) values at peak responsivity of UPD under zero operation bias are reported in Table I Sample B was only characterized electrically, but the current-voltage characteristics were recorded at different gate biases Compared in Figure are the average I-V characteristics at 120 K of five diodes from each category: UPD, UGD, and GD The electrical performance of UGDs is better than that of UPDs, showing the effectiveness of SiO2 passivation At zero gate bias, GDs are leakier and have higher dark current density than that of UGDs This is probably because the metal workfunction and FIG (Color online) Electrical performance comparison between UPDs, UGDs, and GDs Modeled decomposition of dark current density and RA into contributing bulk mechanisms was performed for GDs The inset represents the RA of GDs at À0.5 V under different gate bias the semiconductor workfunction are different, and this misalignment further bends the conduction band at the insulator/ T2SL interface downward, resulting in additional electron accumulation and more severe surface leakage However, when gated bias is applied, electrical performance of the device is significantly improved as predicted Evolution of the dynamic differential resistance area product (RA) of GDs at À0.5 V operation bias as a function of different gate biases are shown in the inset of Figure The improvement is saturated at VG ¼ À40 V when all accumulated electrons on the SiO2-T2SL interface are repelled, restoring flat energy band configuration at mesa sidewalls Due to the dielectric breakdown at À75 volt, with increasing gate bias, the phenomenon of energy band bending up, resulting in holes accumulation and serve surface leakage current, is not observed At saturated level, the dark current density of GDs is around orders of magnitude lower than the UPDs and UGDs for operation bias beyond À1 V After suppressing surface leakage, the measured current approaches the bulk material performance I-V modeling can thus be utilized to reveal different bulk dark current mechanisms In this work, we applied analytical expressions of diffusion, generation-recombination, and trap-assisted tunneling currents as described in Ref 14 Excellent fitting of I-V and RA-V curves was achieved (Figure 2) At 120 K, the detector is dominated by the diffusion mechanism for low bias regime, while trap-assisted tunneling becomes dominant at V < À1.5 Volt While the trend and contribution of each mechanism is clear, the exact values used for fitting may have a wide range, and therefore, further experimental verification of the fitted values is needed This is because each mechanism consists of several unknown fitting parameters that have interchangeable role For example, the diffusion current depends on the product of the doping level and the carrier lifetime It is impossible to extract one parameter without knowing the other Moreover, homojunction dark current expressions were used while in reality, the device architecture is more complicated Nevertheless, the shapes of the I-V curves retain the identity of each dark current mechanism and we can qualitatively distinguish the dominant dark current mechanism from one another This can only be done when surface leakage is no longer dominant Therefore, gating technique is crucial in suppressing the surface leakage and determining the real limiting mechanism in the bulk material As diffusion current is the most sensitive mechanism to temperature, a device with diffusion limited dark current at 120 K means that diffusion current will remain dominant at Downloaded 02 Nov 2011 to 129.105.215.146 Redistribution subject to AIP license or copyright; see http://apl.aip.org/about/rights_and_permissions 183503-3 Chen et al Appl Phys Lett 99, 183503 (2011) FIG (Color online) Temperature dependent current-voltage and resistance-voltage measurements of UGD (dot-dash) and GD (solid-line) under saturated gate bias and model result (circle) between 110 K and 180 K higher temperatures This is seen in the fitting of dark current density and RA of GDs (solid-line) at saturation gated bias (VG ¼ À40 V) and UGDs (dot-dash-line) at different temperatures (Figure 3) Above 150 K, the dark current density of UGDs and saturated GDs are similar (180 K curve at Figure 3(c)), which means at high temperature, the effect of diffusion current surpasses the surface leakage However, significant change in the RA curve can still be observed at 180 K Accordingly, even though surface leakage is not dominated, its effect is still non-negligible and affects the thermal noise and detectivity of a device, which are related to the RA value of a detector From 150 K to 110 K, as the temperature decreases, the effect of gating technique on dark current density becomes more significant—the difference of dark current density at reverse bias between the saturated GDs and UGDs becomes more notable The surface leakage turns out not as sensitive with temperature as bulk diffusion, and thus, it affects a detector’s performance more severely at low temperature At 110 K, the saturated GD dark current density reaches system noise level, 100 pA, for bias from to À200 mV The real dark current density near zero bias should be lower than 100 pA Temperature dependent specific detectivities (D*) for UPDs, UGDs, and GDs are calculated based on their electrical measurements and UPDs quantum efficiency which is representative for the device structure in front side illumination (Table I) D* of UGDs is slightly better than UPDs in the whole temperature range At 180 K and 150 K, D* of GDs is 10% higher than that of UGDs As temperature decreases below 150 K, D* of GDs starts deviating from UGDs At 130 K, D* of GDs is 1.3 times higher than UGDs; at 120 K, it is times higher; and at 110 K, D* of GDs attains 2.5  1014 cm Hz1/2/W (or Jones), which is 3.6 times higher than UGDs Since the dark current density and RA at 110 K are limited by the measurement system, the real D* of GDs at 110 K should be even higher In summary, MWIR T2SL M-barrier photodetector’s performance is limited by surface leakage in low temperature regime The gating technique efficiently reduced the surface leakage and increased the D* from  1013 Jones to 2.5  1014 Jones at 110 K This observation suggests that at low temperature, surface leakage is the limiting factor with standard processing techniques Therefore, to achieve higher performance focal plane arrays, we should either lower the saturation gate voltage and design a compatible read-out integrated circuit or develop another passivation technique which is as effective as gating technique Most importantly, electrical performance achieved with gating technique enables closer evaluation of bulk current in T2SL p-p-M-n photodiode, thus facilitates further optimization of bulk performance G A Sai-Halasz, R Tsu, and L Esaki, Appl Phys Lett 30, 651 (1971) M Razeghi, U.S Patent 6864552, Focal Plane Arrays in Type-II Superlattice (8 March 2005) B.-M Nguyen, D Hoffman, E K Huang, P Y Delaunay, and M Razeghi, Appl Phys Lett 93, 123502 (2008) E K.-w Huang, D Hoffman, B.-M Nguyen, P.-Y Delaunay, and M Razeghi, Appl Phys Lett 94, 053506 (2009) A Hood, P.-Y Delaunay, D Hoffman, B.-M Nguyen, Y Wei, M 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