... module are q, qbar, set, and reset. The root module instantiates m1, which is a module of type SR_latch. The module m1 instantiates nand gates n1 and n2. Q, Qbar, S, and R are port signals in ... last in a module definition. All components except module, module name, and endmodule are optional and can be mixed and matched as per design needs. Verilog allows multiple modules to be defined ... understand the components of a module shown above, let us consider a simple example of an SR latch, as shown in Figure 4-2. Figure 4-2. SR Latch The SR latch has S and R as the input ports and...