Behaviotal Modeling part 1

... blocks will be as follows. time statement executed 0 m = 1& apos;b0; 5 a = 1& apos;b1; 10 x = 1& apos;b0; 30 b = 1& apos;b0; 35 y = 1& apos;b1; 50 $finish; The initial blocks are typically used for ... be grouped initial begin #5 a = 1& apos;b1; //multiple statements; need to be grouped #25 b = 1& apos;b0; end initial begin #10 x = 1& apos;b0; #25 y = 1& apos;b1; end initial #50 $fi...

Ngày tải lên: 28/10/2013, 22:15

... Figure 11 -1 . Figure 11 -1. NMOS and PMOS Switches In Verilog, nmos and pmos switches are instantiated as shown in Example 11 -1 . Example 11 -1 Instantiation of NMOS and PMOS Switches nmos n1(out, ... tranif1 switch conducts if the control signal is a logical 1. These switches are instantiated as shown in Example 11 -3 . Example 11 -3 Instantiation of Bidirectional Switches tran t...

Ngày tải lên: 20/10/2013, 16:15

... reg_a = 16 'b0; reg_b = reg_a; //initialize vectors #15 reg_a[2] = 1& apos;b1; //Bit select assignment with delay #10 reg_b [15 :13 ] = {x, y, z} //Assign result of concatenation to // part select ... reg_a = 16 'b0; reg_b = reg_a; //Initialize vectors reg_a[2] <= #15 1& apos;b1; //Bit select assignment with delay reg_b [15 :13 ] <= #10 {x, y, z}; //Assign result of conc...

Ngày tải lên: 28/10/2013, 22:15

... 1, y = 1 are to be executed at simulation time 0. However, since x = 1 and y = 1 have #0, they will be executed last. Thus, at the end of time 0, x will have value 1 and y will have value 1. ... 7 -12 illustrates zero delay control. Example 7 -12 Zero Delay Control initial begin x = 0; y = 0; end initial begin #0 x = 1; //zero delay control #0 y = 1; end In Ex...

Ngày tải lên: 07/11/2013, 19:15

... 1& apos;bz; out3 = 1& apos;bz; end 2'b10 : begin out0 = 1& apos;bz; out1 = 1& apos;bz; out2 = in; out3 = 1& apos;bz; end 2'b 11 : begin out0 = 1& apos;bz; out1 = 1& apos;bz; out2 = 1& apos;bz; ... ({s1, s0}) //Switch based on control signals 2'b00 : begin out0 = in; out1 = 1& apos;bz; out2 = 1& apos;bz; out3 = 1& apos;bz; end 2'b 01 : begin out0 = 1&...

Ngày tải lên: 07/11/2013, 19:15

... //Illustration 1: Increment count from 0 to 12 7. Exit at count 12 8. //Display the count variable. integer count; initial begin count = 0; while (count < 12 8) //Execute loop till count is 12 7. ... 'define TRUE 1& apos;b1'; 'define FALSE 1& apos;b0; reg [15 :0] flag; integer i; //integer to keep count reg continue; initial begin flag = 16 &a...

Ngày tải lên: 07/11/2013, 19:15

... i<N; i=i +1) begin: r_loop wire t1, t2, t3; xor g1 (t1, a0[i], a1[i]); xor g2 (sum[i], t1, carry[i]); and g3 (t2, a0[i], a1[i]); and g4 (t3, t1, carry[i]); or g5 (carry[i +1] , t2, ... r_loop[0].g1, r_loop [1] .g1, r_loop[2].g1, r_loop[3].g1 r_loop[0].g2, r_loop [1] .g2, r_loop[2].g2, r_loop[3].g2 // and : r_loop[0].g3, r_loop [1] .g3, r_loop[2].g3, r_loop[3].g3 r_loop[0...

Ngày tải lên: 15/12/2013, 03:15

... w will get values 1 and 2 if x = 1& apos;b0 and y = 1& apos;b1 execute first. Variables z and w will get values 2'bxx and 2'bxx if x = 1& apos;b0 and y = 1& apos;b1 execute last. Thus, ... //Example 1: Parallel blocks with delay. reg x, y; reg [1: 0] z, w; initial fork x = 1& apos;b0; //completes at simulation time 0 #5 y = 1& apos;b1; //completes at simulation...

Ngày tải lên: 15/12/2013, 03:15

... 0 010 , B= 010 1, C_IN= 0, C_OUT= 0, SUM= 011 1 15 A= 10 01, B =10 01, C_IN= 0, C_OUT= 1, SUM= 0 010 20 A= 10 10, B =11 11, C_IN= 0, C_OUT= 1, SUM= 10 01 25 A= 10 10, B= 010 1, C_IN= 1, , C_OUT= 1, SUM= ... select signals is tested. IN0= 1, IN1= 0, IN2= 1, IN3= 0 S1 = 0, S0 = 0, OUTPUT = 1 S1 = 0, S0 = 1, OUTPUT = 0 S1 = 1, S0 = 0, OUTPUT = 1 S1 = 1, S...

Ngày tải lên: 15/12/2013, 03:15

... vector nets. addr is a 16 -bit vector net // addr1 and addr2 are 16 -bit vector registers. assign addr [15 :0] = addr1_bits [15 :0] ^ addr2_bits [15 :0]; // Concatenation. Left-hand side is a concatenation ... in1 or in2 will result in a delay of 10 time units before recomputation of the expression in1 & in2, and the result will be assigned to out. If in1 or in2 changes value ag...

Ngày tải lên: 26/01/2014, 14:20