Ebook Computer organization and design (4th edition) Part 2

... 11 -7 11 -8 11 -9 11 -10 11 -11 11 -12 11 -13 11 -14 11 -15 11 -16 11 -17 11 -18 11 -19 11 -20 11 - 21 11- 22 11 -23 11 -24 11 -25 11 -26 11 -27 11 -28 11 -29 Adding Memory to a Digital Logic Circuit 217 States of ... Binary value 00000 000 01 00 010 00 011 0 010 0 0 010 1 0 011 0 0 011 1 010 00 Decimal value 10 11 12 13 14 15 16 17 Binary value 010 01 010 10...

Ngày tải lên: 15/05/2017, 18:09

... example, Figure 9 -2 presents the bitwise AND of the binary values 0110101 12 and 1101101 02 Value Value Resulting AND 1 1 0 1 1 0 1 1 0 Figure 9 -2 Bitwise AND of 0110101 12 and 1101101 02 Remember that ... 166 Computer Organization and Design Fundamentals 3510 = 0010001 12 9310 = 0101110 12 124 10 = 0111110 02 3010 = 0001111 02 This reduces our odd/even detecti...

Ngày tải lên: 15/05/2017, 18:09

... 0.5 1. 0 Program P2 1. 0 0 .1 0.02 10 .0 1. 0 0.2 50.0 5.0 1. 0 Arithmetic mean 1. 0 5.05 10 . 01 5.05 1. 0 1. 1 25.03 2.75 1. 0 Geometric mean 1. 0 1. 0 0.63 1. 0 1. 0 0.63 1. 58 1. 58 1. 0 Total time 1. 0 0 .11 0.04 ... 1. 3 discusses some of the long-term trends in DRAM cost 80 16 MB 70 60 50 Dollars per DRAM chip MB MB 40 256 KB 30 Final chip cost 64 KB 20 10 16 KB...

Ngày tải lên: 07/08/2014, 23:20

... PC←name; ((PC+4) 22 5) ≤ name < ((PC+4) +22 5) JAL name Jump and link Regs[R31]←PC+4; PC←name; ((PC+4) 22 5) ≤ name < ((PC+4) +22 5) JALR R2 Jump and link register Regs[R31]←PC+4; PC←Regs[R2] JR Jump register ... return, jmp ind 0.6% 1.9% shift 2. 0% 0 .2% and 0.4% 0.3% 0.1% 0.1% 0.1% 1% 2. 3% 2% 0.3% 1.3% 0 .2% or 2. 4% 0% 0.1% 0% 21 .6% 23 % other (xor, not) 0% load FP 23 .3% 1...

Ngày tải lên: 07/08/2014, 23:20

... stalls are much higher and the figures more complex 12 3. 9 207 Putting It All Together: The MIPS R4000 Pipeline Clock cycle Operation Issue/stall 25 26 27 28 29 30 31 32 33 34 35 Divide issued in ... described in Figures 3. 43 and 3. 44 If structural hazards are due to write-back contention, assume the earliest instruction gets priority and other instructions are stalled a [15...

Ngày tải lên: 07/08/2014, 23:20

... SD -16(R1),F12 SD -40 (R1),F 24 ADDD F 24, F22,F2 SD - 24( R1),F16 SD -32(R1),F20 ADDD F8,F6,F2 ADDD F16,F 14, F2 ADDD F20,F18,F2 SD 0(R1),F4 ADDD F4,F0,F2 ADDD F12,F10,F2 LD F26, -48 (R1) SD 8(R1),F28 ... unrolling and scheduling work on a superscalar version of DLX with the delays in clock cycles from Figure 4. 2 on page 2 24 4. 4 EXAMPLE Below is the loop we unrolled and scheduled...

Ngày tải lên: 07/08/2014, 23:20

... 64K 256 K 16 42 7.321 4 .59 9 2. 655 1. 857 1. 458 32 44 6.870 4.186 2.263 1 .59 4 1.308 64 48 7.6 05 4.360 2.267 1 .50 9 1.2 45 128 56 10.318 5. 357 2 .55 1 1 .57 1 1.274 256 72 16.847 7.847 3.369 1.828 1. 353 ... Eight-way 7. 65 6.60 6.22 5. 44 5. 90 4.90 4.62 4.09 4.60 3. 95 3 .57 3.19 3.30 3.00 2.87 2 .59 16 2. 45 2.20 2.12 2.04 32 2.00 1.80 1.77 1.79 64 1.70 1.60 1 .57 1 .59 128...

Ngày tải lên: 07/08/2014, 23:20

... write (ns) 60 0 500 400 300 64 12 25 51 10 24 20 48 40 96 81 16 38 32 76 65 13 36 10 26 72 21 52 44 10 288 48 20 57 97 15 32 16 200 Stride 4K 16K 32K 128K 256K 512K 1M FIGURE 5.54 8K 64 K 2M 4M ... Architecture (1988) 6. 1 485 6. 2 Types of Storage Devices 4 86 6.3 Buses—Connecting I/O Devices to CPU/Memory 4 96 6.4 I/O Performance Measures 504 6. 5 Reliability, Availability, a...

Ngày tải lên: 07/08/2014, 23:20

... (19 67) 7. 1 Introduction 563 7. 2 A Simple Network 565 7. 3 Connecting the Interconnection Network to the Computer 573 7. 4 Interconnection Network Media 576 7. 5 Connecting More Than Two Computers 579 ... 608 7. 10 Putting It All Together: An ATM Network of Workstations 613 7. 11 Fallacies and Pitfalls 622 7. 12 Concluding Remarks 625 7. 13 Historical Perspective and Referenc...

Ngày tải lên: 07/08/2014, 23:20