analog bicmos design practices and pitfalls phần 4 docx
analog bicmos design practices and pitfalls phần 4 docx
... equations:
v
4
= i
o
r
o4
(3.28)
v
gs3
= v
bs3
= −v
4
(3.29)
v
o
=(i
o
− gm
3
v
gs3
− gm
b
v
bs3
)r
o3
+ v4 (3.30)
Substituting and rewriting gives
v
o
= i
o
(1 + gm
3
r
o4
+ gm
b3
r
o4
)r
o3
+ i
o
r
o4
(3.31)
Then
r
o
=
V
o
I
o
= ... exercise 14.
References
[1] Baker, R. Jacob, et al, CMOS Circuit Design, Layout and Simu-
lation, IEEE Press, New York, c. 1998.
[2] Gray, Paul R., a...
analog bicmos design practices and pitfalls phần 10 pdf
... 12.5 V?
chapter 9
Design Practices
Component matching and the protection from electrostatic discharge are
important design practices. Accurate component matching reduces costs
and improves circuit ... sheet
resistance. The sheet resistances at R
1
and R
4
are 3 and 9 totaling 12.
This matches the total of the sheet resistances at R
2
and R
3
(5 and 7).
Lateral variations...
analog bicmos design practices and pitfalls phần 1 potx
... silicon.
2.4SimpleSmallSignalModelsforHand
Calculations
2 .4. 1BipolarSmallSignalModel
2 .4. 2OutputImpedance
2 .4. 3SimpleMOSSmallSignalModel
2.5ChapterExercises
3CurrentSources
3.1CurrentMirrorsinBipolarTechnology
3.2CurrentMirrorsinMOSTechnology
ChapterExercises
4VoltageReferences
4. 1SimpleVoltageReferences
4. 2VbeMultiplier
4. 3ZenerVoltageReference
4. 4TemperatureCharacteristicsofI...
analog bicmos design practices and pitfalls phần 2 doc
... −
n
p
(0)
W
B
(1 .46 )
Using Equation 1 .46 in Equation 1 .45 ,
I
c
= I
s
e
V
be
V
T
(1 .47 )
where
I
s
=
A
E
qD
n
n
2
i
W
B
N
D
(1 .48 )
and where N
D
is the base doping, donors per cm
3
.
Equation 1 .47 describes ... of NMOS and PMOS transistors
is useful in the design of analog and digital circuits.
Figure 1.15 CMOS structure.
1.6.1 Simple MOS Model
A simple model for the MOS tra...
analog bicmos design practices and pitfalls phần 3 pps
... McGraw-Hill, New York,
1988.
[4] P.R. Gray and R.G. Meyer, Analysis and Design of Analog Inte-
grated Circuits, 2nd edition, Wiley, New York, c. 19 84, pp. 1-5.
[5] R.S. Muller and T.I. Kamins, Device ... voltage in-
creases. T F
References
[1] P.R. Gray and R.G. Meyer, Analysis and Design of Analog Inte-
grated Circuits, 2nd edition, Wiley, New York, c. 19 84, pp. 1-5.
Fig...
analog bicmos design practices and pitfalls phần 5 potx
... value
of η.
Figure 4. 4 Simulation showing temperature variation and η dependence of
the bandgap voltage V
ref
. η describes the temperature variation of mobility.
(See Equation 4. 1)
4. 5 Bandgap Voltage ... Simple Three-Terminal IC Bandgap Reference,
IEEE Journal of Solid State Circuits, Volume SC-9, No. 6, Decem-
ber 19 74.
[2] P.R. Gray and R.G. Meyer, Analysis and Design of...
analog bicmos design practices and pitfalls phần 6 pps
... I
2
and I
3
?
References
[1] Baker, R. Jacob, et al, CMOS Circuit Design, Layout and Simu-
lation, IEEE Press, New York, c. 1998.
[2] Gray, Paul R., and Mayer, Robert G., Analysis and Design of
Analog ... John Wiley and Sons, Inc.,
New York, c. 19 84.
[3] Millman, Jacob, and Grabel, Arvin, Microelectronics, 2nd edition,
McGraw-Hill Book Company, New York, c. 1987.
[4] Soclo...
analog bicmos design practices and pitfalls phần 7 potx
... 1997.
[3] Gray, Paul R., and Mayer, Robert G., Analysis and Design of
Analog Integrated Circuits, 2nd edition, John Wiley and Sons, Inc.,
New York, c. 19 84.
[4] Millman, Jacob, and Grabel, Arvin, ... I
C
(N1) = 100µA, or I
C
(N1) = 49 .505µA
Then I
C
(N2) = I
C
(P 2) =49 .505µA and I
C
(P 1)=50 .49 5µA.
The difference between V
1
and V
2
is
V
dif
= (26mV )ln
50 .49 5µA...
analog bicmos design practices and pitfalls phần 8 ppsx
... R., and Mayer, Robert G., Analysis and Design of
Analog Integrated Circuits, 2nd edition, John Wiley and Sons, Inc.,
New York, c. 19 84.
[3] Millman, Jacob, and Grabel, Arvin, Microelectronics, ... characteristic for 4. 5V<V
I
< 4. 2V .
References
[1] Baker, R. Jacob, et al., CMOS Circuit Design, Layout and Simu-
lation, IEEE Press, New York, c. 1998.
[2] Gray, Paul R.,...
analog bicmos design practices and pitfalls phần 9 pdf
... V for the 14 V process, and 12.27 V for the 30 V process
Figure 8.23 A small current turns on the base-emitter diode of P
4
and
clamps the base of P
2
one V
be
above the base of P
4
.
8.5 Latchup
Parasitic ... P
2
and N
1
are off. The current source turns P
4
on and V
n
is one
V
be
above V
ref
. When P
2
is on, N
1
is also on. N
1
sinks the current
source and pulls current fro...