analog bicmos design practices and pitfalls phần 1 potx
analog bicmos design practices and pitfalls phần 1 potx
... width and length. The sheet
b) From Equation 1. 22, we have, for the p-region
0.638 +10 =
qx
2
p
N
2
A
2
1
10
15
+
1
10
16
10 .638
1. 1
2
qN
A
= x
2
p
x
p
=3.5x10
−4
cm =3.5µm
From Equation 1. 13, ... conduction and valence bands. The Fermi
level shown corresponds to n-type silicon.
Practices and Pitfalls
Analog
BiCMOS
DESIGN
Contents
1Devices
1. 1Introducti...
analog bicmos design practices and pitfalls phần 5 potx
... 80µA and R
1
should
equal about 3.7K. The drop across R
1
is 2IR
1
=2x10x10
−6
x3.7x10
3
=
0.6V .
The bandgap voltage V
bg
is 0.6+V
be
2
=0.6+0.65 = 1. 25V .
Feedback Mechanism
Transistors N
1
, ... with
respect to temperature and setting it equal to zero and rearranging terms
2
R
1
R
2
ln[n]=
0.002
8.62x10
−5
R
1
R
2
=
11 .6
ln[n]
If n =4,
R
1
R
2
=8.4.
Example
Fortheba...
analog bicmos design practices and pitfalls phần 7 potx
... −
I
C
(P 1)
1. 02
=23.4µA
10 0µA − I
C
(P 1) −
I
C
(P 1)
1. 02
=23.4µA
I
C
(P 1) = 38.679µA
Then I
C
(P 2) = 61. 3 21 A and V
dif
=0.026Vln( 61. 3 21/ 38.679) = 11 .98mV .
The same method can be used to identify ... +85
◦
C?
7.ForthecomparatorinFigure6 .11 , assumeI
S
= 200E -18 A and β =
10 0. Choose K, R1, R2 and R3 such that the nominal threshold
is 1. 250V ± 1% . Size R1...
analog bicmos design practices and pitfalls phần 10 potx
... and
E .16 4 numbers and, 14 1 14 2, 14 8
gatekeepers and, 13 5, 14 8 15 1
H.323 IDs and, 14 1 14 2, 14 8
call routing, PBX systems and, 15
call processing and, 8–9
international calls and, 10 11
call transformations, ... Controller (MC), 11 6
Multipoint Controller Units (MCUs), 48,
11 6 11 7
cascading, 10 2, 11 7 11 9
IP/VC 3 510 , 11 6, 382
IP/VC 3540, 11 6 11 7, 382...
analog bicmos design practices and pitfalls phần 10 pdf
... their ratio is
R
1
R
2
=
R
1
+∆R
1
R
2
+∆R
2
=
1+
∆R1
R
1
1+
∆R
2
R
2
=
1 −
∆W
1
W
1
1 −
∆W
2
W
2
≈ 1 −
∆W
1
− ∆W
2
W
=1
2∆W
W
(9.5)
There is a tradeoff between resistor size and matching, the ... V
o
.
Answer
IftheopampinFigure9 .14 isideal:
V
o
= V
bg
1+
R
1
R
2
In this example, V
bg
=1. 25 V , and R
1
/R
2
= 3 [1 ± .0 01] , (for a 0 .1%
error in the re...
analog bicmos design practices and pitfalls phần 2 doc
... B, and C in Equations 1. 56, 1. 57, and 1. 58:
I
nc
= A
e
V
be
V
T
− e
V
bc
V
T
I
pe
= B
e
V
be
V
T
− 1
(1. 59)
I
pc
= C
e
V
bc
V
T
− 1
Plugging Equations 1. 59 into Equations 1. 53 and 1. 54:
I
E
= ... 1. 11 Ebers-Moll model I
F
= I
ES
(e
V
be
V
T
− 1) I
R
= I
CS
(e
V
bc
V
T
− 1) .
Equations 1. 60 and 1. 61 describe the Ebers-Moll model. A schematic
diag...
analog bicmos design practices and pitfalls phần 3 pps
... area
Ibe1
Kqb
−
Ibc1
Kqb
−
Ibc1
BR
− Ibc2
(2 .15 )
Ibe1=IS exp
V
BE
NF V
T
− 1
(2 .16 )
Ibe2=ISE exp
V
BE
NE V
T
− 1
(2 .17 )
Ibc1=IS exp
V
bc
NR V
T
− 1
(2 .18 )
Ibc2=ISC exp
V
bc
NC V
T
− 1
(2 .19 )
Kqb ... exp
V
bc
NC V
T
− 1
(2 .19 )
Kqb = Kq1
1+ (1+ 4Kq2)
NK
2
(2.20)
where Kq1 describes the Early effect
Kq1=
1
1 −
Vbc
VAF
−
Vbe
VAR
and Kq2 describes...
analog bicmos design practices and pitfalls phần 4 docx
... equation:
I
c
= I
s
e
V
be
V
T
1+
V
ce
V
A
(3 .11 )
and
V
be
(Q2) = V
T
ln
15 0E − 6
200E − 18
=0. 710 9V
Solving the KVL equation, we find
R =
V
be
(Q2) − V
be
(Q1)
97.525µA
= 11 5Ω
NotethatplacingaresistorintheemitterofQ2asshowninFigure3.6
would ... diode-connected it is modeled as 1/ gm
1
. The quantity r
b
is defined as β/gm. Since r
b
is greater than 1/ gm
1
by a fact...
analog bicmos design practices and pitfalls phần 6 pps
... and common-mode output
signals
v
od
= v
o1
− v
o2
and
v
oc
=
v
o1
− v
o2
2
We can identify v
o1
and v
o2
in terms of v
od
and v
oc
v
o1
=
v
od
2
+ v
oc
and
v
o2
= −
v
od
2
+ v
oc
The differential-mode ... Circuit Design, Layout and Simu-
lation, IEEE Press, New York, c. 19 98.
[2] Gray, Paul R., and Mayer, Robert G., Analysis and Design of
Analog Integrated Circuits, 2nd...
analog bicmos design practices and pitfalls phần 8 ppsx
... output. The opamp
output is
V
o
= V
bg
R
1
+
R
2
R
1
− V
g
R
2
R
1
(8 .1)
whereinFigure8 .1, R
1
, R
2
, V
bg
and V
o
are 10 0 Ohms, 300 Ohms, 1. 2
V and 5 V, respectively.
Remedies
r
AddingaKelvinline,asshowninFigure8.2,by-passestheground
line ... .
References
[1] Baker, R. Jacob, et al., CMOS Circuit Design, Layout and Simu-
lation, IEEE Press, New York, c. 19 98.
[2...
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