ARM System Developer’s Guide phần 6 docx
ARM System Developer’s Guide phần 6 docx
... block.
Offset Registers
0—
−4 r14
−8 r13
−12 r12
− 16 r11
−20 r10
−24 r9
−28 r8
−32 r7
− 36 r6
−40 r5
−44 r4
−48 r3
−52 r2
− 56 r1
60 r0
64 pc + 4
68 spsr
There are four major parts of the PCB that ... —
FRAME_R4 + 16 r4
FRAME_R5 +20 r5
FRAME_R6 +24 r6
FRAME_R7 +28 r7
FRAME_R8 +32 r8
FRAME_R9 + 36 r9
FRAME_R10 +40 r10
FRAME_R11 +44 r11
FRAME_R12 +48 —
FRAME_PSR +52 —
FRAME_LR + 56 —...
ARM System Developer’s Guide phần 3 docx
... Register Numbers
6. 4.2 Using More than 14 Local Variables
6. 4.3 Making the Most of Available Registers
6. 5 Conditional Execution
6. 6 Looping Constructs
6. 6.1 Decremented Counted Loops
6. 6.2 Unrolled ... Unpacking
6. 8 Efficient Switches
6. 8.1 Switches on the Range 0 ≤ x<N
6. 8.2 Switches on a General Value x
6. 9 Handling Unaligned Data
6. 10 Summary
166 Chapter 6 Writi...
ARM System Developer’s Guide phần 4 docx
... 0x78, 0x75, 0x72, 0x6f, 0x6c
DCB 0x69, 0x 66, 0x64, 0x61, 0x5e, 0x5c, 0x59, 0x57
DCB 0x55, 0x52, 0x50, 0x4e, 0x4c, 0x49, 0x47, 0x45
DCB 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3a, 0x38, 0x 36
DCB 0x34, 0x32, ... high-low)
a_3 RN lr ; a bits [127: 96] (a high-high)
; long long mul _64 to64 (long long b, long long c)
mul _64 to64
STMFD sp!, {r4,r5,lr}
; 64 -bit a = 64 -bit b * 64 -bit c
UMULL a_0,...
ARM System Developer’s Guide phần 1 ppt
... xi
Chapter
1
ARM Embedded Systems 3
1.1 The RISC Design Philosophy 4
1.2 The ARM Design Philosophy 5
1.3 Embedded System Hardware 6
1.4 Embedded System Software 12
1.5 Summary 15
Chapter
2
ARM Processor ... Computer
architecture. I. Symes, Dominic. II. Wright, Chris, 1953- III. Title.
QA 76. 76. D47S 565 2004
005.1–dc22
2004040 366
ISBN: 1-55 860 -874-5
For information on all Mor...
ARM System Developer’s Guide phần 2 ppsx
... *Rs.y)+Rn
SMLALxy ( 16- bit * 16- bit)+ 64 -bit 64 -bit — [RdHi, RdLo]+= Rm.x * Rs.y
SMLAWy ((32-bit * 16- bit) 16) + 32-bit 32-bit yes Rd = ((Rm * Rs.y) 16) + Rn
SMULxy ( 16- bit * 16- bit) 32-bit — Rd ... value
ARMv4 LDRSB load a signed 8-bit value
LDRH load an unsigned 16- bit value
LDRSH load a signed 16- bit value
STRH store a signed or unsigned 16- bit value
ARMv5 LDRD load a sign...
ARM System Developer’s Guide phần 5 ppt
... (cycles/FFT) ARM9 E (cycles/FFT)
64 point 3,524 2,480
2 56 point 19,514 13,194
1,024 point 99,9 46 66, 1 96
4,0 96 point 487 ,63 2 318,878
302 Chapter 8 Digital Signal Processing
Table 8.8 ARMv5E IIR timings.
Processor ... 0x7f62,0x0c8c, 0x7d8a,0x18f9
DCW 0x6a6e,0x471d, 0x7d8a,0x18f9, 0x 764 2,0x30fc
DCW 0x5134,0x62f2, 0x7a7d,0x2528, 0x6a6e,0x471d
DCW 0x30fc,0x 764 2, 0x 764 2,0x30fc, 0...
ARM System Developer’s Guide phần 7 pdf
... 0 ARM7 20T, ARM9 20T, ARM9 22T, ARM9 26EJ-S,
ARM1 022E, ARM1 026EJ-S, StrongARM, XScale
Flush data cache MCR p15, 0, Rd, c7, c6, 0 ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM9 40T,
ARM9 46E-S, ARM1 022E, ARM1 026EJ-S,
StrongARM, ... ARM1 022E, ARM1 026EJ-S,
StrongARM, XScale
Flush instruction cache MCR p15, 0, Rd, c7, c5, 0 ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM9 40T,
ARM9 46E-S,...
ARM System Developer’s Guide phần 8 pdf
... invalidate
ARM9 20T, ARM9 22T, ARM9 26EJ-S,
ARM1 022E, ARM1 026EJ-S,
StrongARM, XScale
Invalidate I
TLB by line
MCR p15, 0, Rd, c8, c5, 1 virtual address
to invalidate
ARM9 20T, ARM9 22T, ARM9 26EJ-S,
ARM1 022E, ... ARM9 26EJ-S,
ARM1 022E, ARM1 026EJ-S,
StrongARM, XScale
Invalidate D
TLB
MCR p15, 0, Rd, c8, c6, 0 virtual address
to invalidate
ARM9 20T, ARM9 22T, ARM9 26EJ-S,
A...
ARM System Developer’s Guide phần 9 doc
... beyond ARMv6 563
15.3 ARMv6 Implementations
ARM completed development of ARM1 136J in December 2002, and at this writing con-
sumer products are being designed with this core. The ARM1 136J pipeline ... introduces the first high-performance ARMv6
implementations and, in addition to the ARMv6 technologies, one of ARM s latest
technologies—TrustZone.
549
590 Appendix A ARM and Thumb Asse...
ARM System Developer’s Guide phần 10 ppsx
... that the ARM9 66 E-S processor has a ARM9 E core and
implements ARM architecture version 5TE. Any ARMv5TE binaries will execute on an
ARM9 66 E-S processor.
C.1 ARM Naming Convention
All ARM processors ... if not executed].”
B.1 ARM Instruction Set Encodings
B.2 Thumb Instruction Set Encodings
B.3 Program Status Registers
D.8 ARM1 1 Cycle Timings 66 3
Table D.14 ARM1 1 (ARMv6)...