ARM System Developer’s Guide phần 3 docx

... (N +k)) + 1 for all − 2 N ≤ n<0 (5. 13) For 32 -bit signed n, we take N = 31 and choose k ≤ 31 such that 2 k−1 <d≤ 2 k . This ensures that we can find a 32 -bit unsigned s = (2 N +k + 2 k )/d ... y_1, y_1, x_1, LSL k MOV y_2, x_1, LSR kr ORR y_2, y_2, x_2, LSL k MOV y _3, x_2, LSR kr ORR y _3, y _3, x _3, LSL k MOV y_4, x _3, LSR kr ORR y_4, y_4, x_4, LSL k MOV y_5, x_4, LSR kr ORR...

Ngày tải lên: 09/08/2014, 12:22

... 0x4e, 0x4c, 0x49, 0x47, 0x45 DCB 0x 43, 0x41, 0x3f, 0x3d, 0x3b, 0x3a, 0x38, 0x36 DCB 0x34, 0x32, 0x31, 0x2f, 0x2d, 0x2c, 0x2a, 0x29 DCB 0x27, 0x26, 0x24, 0x 23, 0x21, 0x20, 0x1e, 0x1d DCB 0x1c, ... 0xb02c0b 03, 0x0228193f, 0xac769184, 0x0247883b DCD 0xa8e83f57, 0x02664f8d, 0xa57eb5 03, 0x02847610 DCD 0xa 237 c32b, 0x02a20 231 , 0x9f1165e7, 0x02bef9ff DCD 0x9c09c09c, 0x02db 632 d, 0x991f1a51,...

Ngày tải lên: 09/08/2014, 12:22

... mask 2 9 .3 Interrupt Handling Schemes 33 9 CMP r0,#0 ;3: ifprocessing? LDMNEIA r 13! ,{r0-r3,r12,pc}ˆ ; 4 : else return MRS r2,spsr ; 5 : copy spsr_irq MOV r0,r 13 ; 5 : copy r 13_ irq ADD r 13, r 13, #6*4 ... offset from 0x03ff0000. This is achieved using the following code: sandstone_init1 LDR r3, =SYSCFG ; where SYSCFG=0x03ff0000 LDR r4, =0x03ffffa0 STR r4, [r3] Register r3 contains th...

Ngày tải lên: 09/08/2014, 12:22

... Philosophy 1.2.1 Instruction Set for Embedded Systems 1 .3 Embedded System Hardware 1 .3. 1 ARM Bus Technology 1 .3. 2 AMBA Bus Protocol 1 .3. 3 Memory 1 .3. 4 Peripherals 1.4 Embedded System Software 1.4.1 Initialization ... Register 22 2 .3 Pipeline 29 2.4 Exceptions, Interrupts, and the Vector Table 33 2.5 Core Extensions 34 2.6 Architecture Revisions 37 2.7 ARM Processor F...

Ngày tải lên: 09/08/2014, 12:22

... to the Thumb Instruction Set r3 = 0x000000 03 r4 = 0x9000 STMIA r4!,{r1,r2,r3} POST mem32[0x9000] = 0x00000001 mem32[0x9004] = 0x00000002 mem32[0x9008] = 0x000000 03 r4 = 0x900c ■ 4.7 Stack Instructions The ... instructions are translated into a pair of 16-bit 70 Chapter 3 Introduction to the ARM Instruction Set 3. 3 .3. 1 Stack Operations The ARM architecture uses the load-store mul...

Ngày tải lên: 09/08/2014, 12:22

... 22.0 ARM9 TDMI 7.0 4.8 8 .3 22.0 StrongARM 4.8 3. 8 5.2 16.5 ARM9 E 2.5 1 .3 4 .3 8.0 XScale 1.8 1 .3 3.7 7.7 Table 8.10 ARM FFT benchmarks. 16-bit complex FFT (radix-4) ARM9 TDMI (cycles/FFT) ARM9 E ... c _32 , a_2 SMLATB a _3, x_54, c _32 , a _3 SMLABB a_4, x_10, c _32 , a_4 SMLATB a_5, x_10, c _32 , a_5 SMLATT a_0, x _32 , c _32 , a_0 LDR x _32 , [x], #4 SMLABT a_1, x_54, c _32...

Ngày tải lên: 09/08/2014, 12:22

... ARM9 26EJ-S, ARM1 022E, ARM1 026EJ-S, StrongARM, XScale Flush data cache MCR p15, 0, Rd, c7, c6, 0 ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM9 40T, ARM9 46E-S, ARM1 022E, ARM1 026EJ-S, StrongARM, XScale Flush instruction ... XScale Flush instruction cache MCR p15, 0, Rd, c7, c5, 0 ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM9 40T, ARM9 46E-S, ARM1 022E, ARM1 026EJ-S, StrongARM, XScale ■ fl...

Ngày tải lên: 09/08/2014, 12:22

... 0xFFFF0000 15612 234 78910 0 MCWRS 31 ARM7 20T 161112 237 8910 0 IMCRS 31 ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM1 026EJ-S 13 V 14 13 V 14 54 11 161112 237 8910 0 IMCRS 31 ARM1 022E 13 V 14 54 W Figure 14. 13 CP15:c1 ... invalidate ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM1 022E, ARM1 026EJ-S, StrongARM, XScale Invalidate I TLB by line MCR p15, 0, Rd, c8, c5, 1 virtual address t...

Ngày tải lên: 09/08/2014, 12:22

... beyond ARMv6 5 63 15 .3 ARMv6 Implementations ARM completed development of ARM1 136 J in December 2002, and at this writing con- sumer products are being designed with this core. The ARM1 136 J pipeline ... change this bit (ARMv4T and above). mode The current processor mode. See Table B.4. SEL Rd, Rn, Rm Rd [31 :24] = GE [3] ? Rn [31 :24] : Rm [31 :24] Rd[ 23: 16] = GE[2] ? Rn[ 23: 16]...

Ngày tải lên: 09/08/2014, 12:22

... ARMv6 2. USADA8<cond> Rd, Rm, Rs, Rn ARMv6 Action 1. Rd = abs(Rm [31 :24]-Rs [31 :24]) + abs(Rm[ 23: 16]-Rs[ 23: 16]) + abs(Rm[15:08]-Rs[15:08]) + abs(Rm[07:00]-Rs[07:00]) 2. Rd = Rn + abs(Rm [31 :24]-Rs [31 :24]) ... cycles if not executed].” B.1 ARM Instruction Set Encodings B.2 Thumb Instruction Set Encodings B .3 Program Status Registers D.8 ARM1 1 Cycle Timings 6 63 Table D.14...

Ngày tải lên: 09/08/2014, 12:22