ARM System Developer’s Guide phần 2 ppsx

... register r0. PRE r0 = 0x00000000 r1 = 0x000000 02 r2 = 0x000000 02 MUL r0, r1, r2 ; r0 = r1*r2 POST r0 = 0x00000004 r1 = 0x000000 02 r2 = 0x000000 02 ■ The long multiply instructions (SMLAL, SMULL, ... lower 32 bits, and register r1 contains the higher 32 bits of the 64-bit result. PRE r0 = 0x00000000 r1 = 0x00000000 r2 = 0xf00000 02 r3 = 0x000000 02 UMULL r0, r1, r2, r3 ; [r1,r0] = r...

Ngày tải lên: 09/08/2014, 12:22

... Registers Table B.6 shows how to decode the 32- bit program status registers for ARMv6. Table B.6 cpsr and spsr decode table. 313 029 2 827 2 625 2 423 222 120 19181716151413 121 110987654 321 0 N ZCVQ Res J Res GE[3:0] Res ... ARM instruction decode table. Instruction classes (indexed by op) 313 029 2 827 2 625 2 423 22 2 120 19181716151413 121 11098 7 65 4 321 0 AND | EOR | SUB | RSB | c...

Ngày tải lên: 09/08/2014, 12:22

... Fundamentals 19 2. 1 Registers 21 2. 2 Current Program Status Register 22 2. 3 Pipeline 29 2. 4 Exceptions, Interrupts, and the Vector Table 33 2. 5 Core Extensions 34 2. 6 Architecture Revisions 37 2. 7 ARM Processor ... xi Chapter 1 ARM Embedded Systems 3 1.1 The RISC Design Philosophy 4 1 .2 The ARM Design Philosophy 5 1.3 Embedded System Hardware 6 1.4 Embedded System...

Ngày tải lên: 09/08/2014, 12:22

... following mathematical results: 1 If 2 N +k ≤ ds ≤ 2 N +k + 2 k , then n/d = (ns)  (N + k) for 0 ≤ n< ;2 N . (5.8) If 2 N +k − 2 k ≤ ds < 2 N +k , then n/d = (ns + s)  (N + k) for 0 ≤ n< ;2 N . (5.9) 1. For ... comparison. str_tolower LDRB r2,[r1],#1 ; c = *(in++) SUB r3,r2,#0x41 ; r3 = c -‘A’ CMP r3,#0x19 ; if (c <=‘Z’-‘A’) ADDLS r2,r2,#0x20 ; c +=‘a’-‘A’ STRB r2,[r...

Ngày tải lên: 09/08/2014, 12:22

... 0xbc 526 40c, 0x01c592fb DCD 0xb81702e0, 0x01e 726 aa, 0xb40b40b4, 0x 020 7fb51 DCD 0xb02c0b03, 0x 022 8193f, 0xac769184, 0x 024 7883b DCD 0xa8e83f57, 0x 026 64f8d, 0xa57eb503, 0x 028 47610 DCD 0xa237c32b, 0x02a2 023 1, ... 2 28 <d2 − 32 . Case 3.3 25 6 <d<5 12 Then f 0 ≤ 1 implies |e 0 | 2 −6 .Asf 1 = g 1 = 0, it follows that e 2 1 ≤ 2 24 <d2 − 32 . Case 3.4 5 12 ≤...

Ngày tải lên: 09/08/2014, 12:22

... (cycles/biquad) ARM7 TDMI 7.6 5 .2 9.0 22 .0 ARM9 TDMI 7.0 4.8 8.3 22 .0 StrongARM 4.8 3.8 5 .2 16.5 ARM9 E 2. 5 1.3 4.3 8.0 XScale 1.8 1.3 3.7 7.7 Table 8.10 ARM FFT benchmarks. 16-bit complex FFT (radix-4) ARM9 TDMI (cycles/FFT) ... c_ 32, a _2 SMLATB a_3, x_54, c_ 32, a_3 SMLABB a_4, x_10, c_ 32, a_4 SMLATB a_5, x_10, c_ 32, a_5 SMLATT a_0, x_ 32, c_ 32, a_0 LDR x_ 32, [x], #4...

Ngày tải lên: 09/08/2014, 12:22

... +4— FRAME_R2 +8— FRAME_R3 + 12 — FRAME_R4 +16 r4 FRAME_R5 +20 r5 FRAME_R6 +24 r6 FRAME_R7 +28 r7 FRAME_R8 + 32 r8 FRAME_R9 +36 r9 FRAME_R10 +40 r10 FRAME_R11 +44 r11 FRAME_R 12 +48 — FRAME_PSR + 52 — FRAME_LR ... Process control block. Offset Registers 0— −4 r14 −8 r13 − 12 r 12 −16 r11 20 r10 24 r9 28 r8 − 32 r7 −36 r6 −40 r5 −44 r4 −48 r3 − 52 r2 −56 r1 −60 r0 −64 pc + 4 −68 spsr...

Ngày tải lên: 09/08/2014, 12:22

... ARM9 20 T, ARM9 22 T, ARM9 26 EJ-S, ARM1 022 E, ARM1 026 EJ-S, StrongARM, XScale Flush data cache MCR p15, 0, Rd, c7, c6, 0 ARM9 20 T, ARM9 22 T, ARM9 26 EJ-S, ARM9 40T, ARM9 46E-S, ARM1 022 E, ARM1 026 EJ-S, StrongARM, ... XScale Flush instruction cache MCR p15, 0, Rd, c7, c5, 0 ARM9 20 T, ARM9 22 T, ARM9 26 EJ-S, ARM9 40T, ARM9 46E-S, ARM1 022 E, ARM1 026 EJ-S, S...

Ngày tải lên: 09/08/2014, 12:22

... invalidate ARM9 20 T, ARM9 22 T, ARM9 26 EJ-S, ARM1 022 E, ARM1 026 EJ-S, StrongARM, XScale Invalidate I TLB by line MCR p15, 0, Rd, c8, c5, 1 virtual address to invalidate ARM9 20 T, ARM9 22 T, ARM9 26 EJ-S, ARM1 022 E, ... table at 0xFFFF0000 156 12 23478910 0 MCWRS 31 ARM7 20 T 1611 12 2378910 0 IMCRS 31 ARM9 20 T, ARM9 22 T, ARM9 26 EJ-S, ARM1 026 EJ-S 13 V 14 1...

Ngày tải lên: 09/08/2014, 12:22

... r2, r2 ; r0 = r2 + r2 and flags updated ADD r0, r0, r0, LSL #1 ; r0 = 3*r0 ADD pc, pc, r0, LSL #2 ; skip r0+1 instructions ADD r0, r1, r2, ROR r3 ; r0 = r1 + ((r2 >> r3)|(r2 << ( 32- r3)) ADDS ... Rd, Cn, Cm {, <op2>} ARMv2 2. MCR2 <copro>, <op1>, Rd, Cn, Cm {, <op2>} ARMv5 3. MCRR<cond> <copro>, <op1>, Rd, Rn, Cm ARMv5E 4. MCRR2 <cop...

Ngày tải lên: 09/08/2014, 12:22