ARM System Developer’s Guide phần 1 ppt
ARM System Developer’s Guide phần 1 ppt
... Contents
Chapter
11
Embedded Operating Systems 3 81
11. 1 Fundamental Components 3 81
11. 2 Example: Simple Little Operating System 383
11 .3 Summary 400
Chapter
12
Caches 403
12 .1 The Memory Hierarchy ... xi
Chapter
1
ARM Embedded Systems 3
1. 1 The RISC Design Philosophy 4
1. 2 The ARM Design Philosophy 5
1. 3 Embedded System Hardware 6
1. 4 Embedded System Softwar...
ARM System Developer’s Guide phần 5 ppt
... 8.0
ARM1 0E 45 11 .2
XScale 30 7.7
SMLABT s_0, b1_s _1, b1_a 21, x _1
SMLABB x _1, b1_s_2, b1_b 21, s_0
SMLABT x _1, b1_s _1, b1_b 21, x _1
MOV b1_s _1, s_0, ASR #14
MOV x_0, x_0, ASR #14
MOV x _1, x _1, ASR ... biquad 1, packed -a[2], -a [1]
b1_b 21 RN 11 ; biquad 1, packed +b[2], +b [1]
b1_s _1 RN 12 ; biquad 1, s[t -1]
b1_s_2 RN 14 ; biquad 1, s[t-2]
; typedef struct {
;...
ARM System Developer’s Guide phần 2 ppsx
... ARM Instruction Set
mem32[0x80 010 ] = 0x 01
r0 = 0x00080 010
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
LDMIA r0!, {r1-r3}
POST r0 = 0x0008001c
r1 = 0x000000 01
r2 = 0x00000002
r3 = 0x00000003
Figure ... section.
0x80020
0x8001c
0x80 018
0x80 014
0x80 010
0x8000c
0x00000005
0x00000004
0x00000003
0x00000002
0x000000 01
0x00000000
r3 = 0x00000000
r2 = 0x00000000
r1 = 0x00000000
r...
ARM System Developer’s Guide phần 3 docx
... data
checksum_loop
LDR r1,[r0],#4 ; r1 = *(data++)
ADD r4,r1,r4 ; sum += r1
LDR r1,[r13,#4] ; r1 = N (read from stack)
SUBS r1,r1, #1 ; r1 & set flags
STR r1,[r13,#4] ;N=r1(write to stack)
BNE ... y
1
. In general, we can assign x
n
to the same register as y
n +1
. Therefore,
assign
x_0 RN 5
x _1 RN 6
x_2 RN 7
x_3 RN 8
x_4 RN 9
x_5 RN 10
x_6 RN 11
x_7 RN 12
y_0 RN 4
y _1 RN x_...
ARM System Developer’s Guide phần 4 docx
... d.
di
0
g
0
e
0
2
32
e
2
1
2, 4, 8, 16 64 1 2
−8
1
3, 6, 12 96 2//3 2
−8
1
5, 10 80 4//5 2
−8
1
7, 14 11 2 2//7 2
−9
< ;1
9 72 5//9 5 * 2
11
< ;1
11 88 2/ /11 2
10
< ;1
13 10 4 7/ /13 7 * 2
11
< ;1
15 12 0 8/ /15 ... −
2
N
x
(7.3)
0 .1
0.05
0
−0.05
−0 .1
−0 .15
−0.2
−0.25
0.95 1 1.05
x
0
= 1 x
1
= 1. 2
x
2
=1. 248
x = 1. 25
f(x) = 0.8 − 1/ x
1...
ARM System Developer’s Guide phần 6 docx
... comment
SUB r14, r14, #4 ; r14_irq-=4
STMFD r13!, {r14} ; save r14_irq
MRS r14, spsr ; copy spsr_irq
STMFD r13!,{r10,r 11, r12,r14} ; save context
LDR r14, =ic_Base ; int crtl addr
LDR r10, [r14, #IRQStatus] ... 0xc
interrupt_handler
SUB r14, r14,#4 ; r14_irq-=4
STMFD r13!, {r14} ; save r14_irq
MRS r14, spsr ; copy spsr_irq
STMFD r13!, {r10,r 11, r12,r14} ; save context
LDR r14, =ic_Base ; in...
ARM System Developer’s Guide phần 7 pdf
... ARM9 20T, ARM9 22T, ARM9 26EJ-S,
ARM1 022E, ARM1 026EJ-S, StrongARM, XScale
Flush data cache MCR p15, 0, Rd, c7, c6, 0 ARM9 20T, ARM9 22T, ARM9 26EJ-S, ARM9 40T,
ARM9 46E-S, ARM1 022E, ARM1 026EJ-S,
StrongARM, ... D-cache line by loop MCR p15, 0, r15, c7, c10, 3 ARM9 26EJ-S, ARM1 026EJ-S
Test, clean, and flush D-cache by loop MCR p15, 0, r15, c7, c14, 3 ARM9 26EJ-S, ARM1 026EJ-...
ARM System Developer’s Guide phần 8 pdf
... physical
memory.
14 .9 The Fast Context Switch Extension 519
D0
D7 D6 D5 D4 D3 D2 D1
D8
D15 D14 D13 D12 D 11 D10 D9
010 0 00 00 00 00 01 0000 01 00 00 00 00 00 00
D0D7 D6 D5 D4 D3 D2 D1D8D15 D14 D13 D12 D 11 D10 ... mask)
14 .4 Page Tables 503
Section entry
15 111 2
31
2348 910 1920 0
Base address 1 1 0AP Domain0SBZ C B
Fine page table
Base address 1 1 1
1 511 12
31
234890...
ARM System Developer’s Guide phần 9 doc
... rules, A is bit 1 of system coprocessor register CP15:c1:c0:0, and U
is bit 22 of CP15:c1:c0:0, introduced in ARMv6. If there is no system coprocessor, then
A = U = 0.
■
If A = 1, then unaligned ... LDR<cond>{H|SB|SH} Rd, [Rn], #{-}<immed8> ARMv4
15 .4 Future Technologies beyond ARMv6 563
15 .3 ARMv6 Implementations
ARM completed development of ARM1 13 6J in December...
ARM System Developer’s Guide phần 10 ppsx
... 00 011 op 1 S 0000 Rd shift_size shift 0 Rm
BX | BLX cond 00 010 0 10 111 111 111 111 00op 1 Rm
CLZ cond 00 010 1 10 111 1 Rd 11 110 0 01 Rm
QADD | QSUB | QDADD | QDSUB cond 00 010 op 0 Rn Rd 0000 010 1 Rm
BKPT 11 1000 010 0 ... UXTB 10 110 010 op Lm Ld
REV | REV16 | | REVSH 10 111 010 op Lm Ld
PUSH | POP 10 11op 10 R register_list
SETEND LE | SETEND BE 10 110 110 010 1op 000
CP...