Examples of VHDL Descriptions phần 1 ppt

... OF seg7dec IS BEGIN WITH bcdin SELECT segout <= " ;10 00000" WHEN X"0", " ;11 0 011 1" WHEN X" ;1& quot;, " ;11 011 01& quot; WHEN X"2", "0000 011 " ... " ;10 0" AFTER 10 0 ns, " 010 " AFTER 200 ns, " ;11 0" AFTER 300 ns, "0 01& quot; AFTER 400 ns, " ;10 1" AFTER 500 ns, " 01...

Ngày tải lên: 07/08/2014, 23:20

... addr10 IS NATURAL RANGE 0 TO 10 23; SUBTYPE data16 IS INTEGER RANGE -32768 TO +32767; TYPE ram_array IS ARRAY(addr10'LOW TO addr10'HIGH) OF data16; CONSTANT z_val : data16 := -1; END ... (46 of 67) [23/ 1 /2002 4: 1 5:09 ] Examples of VHDL Descriptions next_state <= s0; else out1 <= &apos ;1& apos;; next_state <= s1; end if; wh...

Ngày tải lên: 07/08/2014, 23:20

... [23/ 1 /2002 4: 1 5:09 ] Examples of VHDL Descriptions in1 => a, in2 => b, out1 => and1_out); or1: org port map( in1 => a, in2 => b, out1 => or1_out); ... structural of adder is signal xor1_out, and1_out, and2_out, or1_out : std_logic; begin xor1: xorg port map( in1 => a, in2 => b, out1 => xor1_out); xor2: xorg port map( in...

Ngày tải lên: 07/08/2014, 23:20

... [23/ 1 /2002 4: 1 5: 1 0 ] Examples of VHDL Descriptions end xorg; architecture only of xorg is begin p1: process(in1, in2) variable val : std_logic; begin val := in1 xor in2; ... " ;11 0"; elsif I(5) = &apos ;1& apos; then A <= " ;10 1"; elsif I(4) = &apos ;1& apos; then A <= " ;10 0"; elsif I(3) = &apos ;1& apos; then A <...

Ngày tải lên: 07/08/2014, 23:20

... OF seg7dec IS BEGIN WITH bcdin SELECT segout <= " ;10 00000" WHEN X"0", " ;11 0 011 1" WHEN X" ;1& quot;, " ;11 011 01& quot; WHEN X"2", "0000 011 " ... [23/ 1 /2002 4: 1 5:08 ] Examples of VHDL Descriptions begin process(in1, in2) begin if in1 = in2 then out1 <= '0' after 10 ns; else...

Ngày tải lên: 08/08/2014, 01:21

... 67) [23/ 1 /2002 4: 1 5:09 ] Examples of VHDL Descriptions tin(i) <= &apos ;1& apos;; end generate; t1_size : if i > 0 generate tin(i) <= q(i -1) and tin(i -1) ; end generate; ... BEGIN http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html ( 1 5 of 67) [23/ 1 /2...

Ngày tải lên: 08/08/2014, 01:21

... [23/ 1 /2002 4: 1 5:09 ] Examples of VHDL Descriptions in1 => a, in2 => b, out1 => and1_out); or1: org port map( in1 => a, in2 => b, out1 => or1_out); ... structural of adder is signal xor1_out, and1_out, and2_out, or1_out : std_logic; begin xor1: xorg port map( in1 => a, in2 => b, out1 => xor1_out); xor2: xorg port map( in...

Ngày tải lên: 08/08/2014, 01:21

... Y20, Y 21, Y22, Y23, Y10, Y 11, Y12, Y13 : out std_logic); end HCT139; architecture VER1 of HCT139 is begin Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR ... ns; http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html ( 1 4 of 67) [23/ 1 /2002 4: 1 5:08...

Ngày tải lên: 07/08/2014, 23:20

... " ;11 00"; CONSTANT lita : BIT_VECTOR(3 DOWNTO 0) := " ;11 01& quot;; CONSTANT litb : BIT_VECTOR(3 DOWNTO 0) := " ;11 10"; CONSTANT clra : BIT_VECTOR(3 DOWNTO 0) := " ;11 11& quot;; ... of 67) [23/ 1 /2002 4: 1 5:09 ] Examples of VHDL Descriptions END version1; Behavioural model of a simple 8-bit CPU LIBRARY ieee; USE ieee.std_l...

Ngày tải lên: 07/08/2014, 23:20

... "0000", " 011 0", " 010 1", " 011 1", " ;11 00", " 010 0", "0000", " 011 0", " 010 1", " 011 1"); END rompac; ... <= s 11; when s 11 => wait for 4th no numled <= " ;11 011 1"; seldisplay <= 2; if next_no = &apos ;1& apos; then lott_ns <= s12; else lott_...

Ngày tải lên: 07/08/2014, 23:20