... in cycle 8.4. B has five delay slots and starts in cycle 3, since branching occurs in cycle 9,after the ADD instruction.5. SUB instruction must start one cycle before the branch instruction, ... four. The accumulation associated with one of the ADDSP instructions at each loop cycle follows:Loop Cycle Accumulator (one ADDSP)1 02 03 04 05 p0 ;first product6 p1 ;second product7 p38 ... following cycles:Cycle 1: LDW, LDW (also initialization of count, and the accumulators A7 and B7)Cycle 2: LDW, LDW, SUBCycles 3–5: LDW, LDW, SUB, BCycles 6–7: LDW, LDW, MPY, MPYH, SUB, BCycles...