... input a, b, c, d; wire e, f; //Delay is distributed to each gate. and #5 a1(e, a, b); and #7 a2(f, c, d); and #4 a3(out, e, f); endmodule //Distributed delays in data flow definition ... module M (out, a, b, c, d); output out; input a, b, c, d; wire e, f; and a1(e, a, b); and a2(f, c, d); and #11 a3(out, e, f);//delay only on the output gate endmodule Lumped delays ... Types of Delay Models There are three types of delay models used in Verilog: distributed, lumped, and pin-to-pin (path) delays. 10.1.1 Distributed Delay Distributed delays are specified on a...