1114 compal la b511p

A B C D E Model Name : Z5W1M File Name : LA-B511P 1 Compal Confidential 2 EA52_BM UMA M/B Schematics Document Intel Bay Trail M 2014-03-13 REV:1.0 3 4 PCB@ DAX PCB 12R LA-B211P REV0 M/B Part Number DA60016I000 Description PCB 12R LA-B511P REV0 M/B Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Page Rev 0.3 Bay Trail M LA-B511P Date: A B C D Thursday, March 13, 2014 Sheet E of 39 A B C D E Memory BUS One Channel 204pin DDR3L-SO-DIMM X1 P.13 1.35V DDR3L 1066/1333 Max speed of DDR3L to 1333MT/s for M sku EDS 1 port port port Touch Panel Conn USB 3.0 Conn P.21 LVDS-Translator RTD2132N P.14 EDP P.16 P.15 CMOS Camera DDI x2 HDMI Conn LCD Conn eDP/LVDS P.15 P.15 LVDS USB3.0 x1 port VALLEYVIEW-M PCIe 2.0 x4 port port port USB2.0 x4 USB HUB GL850G P.21 port SOC LAN(GbE) port RTL8111GUS P.17 WLAN MINI CARD RJ45 conn HUB port1 FCBGA 1170 Pin P.18 P.17 SATA II x2 port HUB port2 HD Audio port SPI HDA Codec USB 2.0 Conn P.21 ALC283 P.20 USB 2.0 Conn P.19 SPI ROM 1.8V (8MB) EC ENE KB9022 SATA HDD Conn HUB port4 Card Reader RTS5170 SD only P.20 BT MINI CARD page 05~12 LPC BUS SATA ODD Conn HUB port3 P.08 P.22 P.20 Int Analog MIC P.19 Universal Jack Sub Board P.19 Int Speaker P.19 Touch Pad Int.KBD P.23 P.23 LS-B471P RTC CKT Card Reader TPM P.08 RTS5170 in (SD) NPCT650 P.18 DC/DC Interface CKT USB 2.0 conn x1 P.24 Power Circuit DC/DC P.25~P.35 USB port LED/Power On/Off P.23 P.21 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: A B C D Thursday, March 13, 2014 Sheet E of 39 A B C Voltage Rails Power Plane Description S0 S3 S4/S5 VIN 19V Adapter power supply ON ON ON BATT+ 12V Battery power supply ON ON ON B+ AC or battery power rail for power circuit (19V/12V) ON ON ON +RTCVCC RTC Battery Power ON ON ON +1.0VALW +1.0v Always power rail ON ON ON +1.8VALW +1.8v Always power rail ON ON ON +3VALW +3.3v Always power rail ON ON ON +5VALW +5.0v Always power rail ON ON ON +1.35V +1.35V power rail for DDR3L ON ON OFF +SOC_VCC Core voltage for SOC ON OFF OFF +SOC_VNN GFX voltage for SOC ON OFF OFF +0.675VS +0.675V power rail for DDR3L Terminator ON OFF OFF +1.0VS +1.0v system power rail ON OFF OFF +1.05VS +1.05v system power rail ON OFF OFF +1.35VS +1.35v system power rail ON OFF OFF +1.5VS +1.5v system power rail ON OFF OFF +1.8VS +1.8v system power rail ON OFF OFF +3VS +3.3v system power rail ON OFF OFF +5VS +5.0v system power rail ON OFF OFF BOM Option Table Item BOM Structure Unpop @ Connector CONN@ EMC requirement EMC@ EMC requirement unpop @EMC@ IOAC support AC@ Choose Analog MIC pop AMIC@ Backlight Keyboard BL@ EDP panel select EDP@ LVDS panel select LVDS@ Power Switch on board DBG@ Jump for transfer power JP@ E Board ID / SKU ID Table for AD channel Vcc Ra/Rc/Re Board ID 10 11 12 13 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 12K +/- 5% 15K +/- 5% 20K +/- 5% 27K +/- 5% 33K +/- 5% 43K +/- 5% 56K +/- 5% 75K +/- 5% 100K +/- 5% 130K +/- 5% 160K +/- 5% 200K +/- 5% 240K +/- 5% V AD_BID V 0.347 V 0.423 V 0.541 V 0.691 V 0.807 V 0.978 V 1.169 V 1.398 V 1.634 V 1.849 V 2.015 V 2.185 V 2.316 V V AD_BID typ V 0.354 V 0.430 V 0.550 V 0.702 V 0.819 V 0.992 V 1.185 V 1.414 V 1.650 V 1.865 V 2.031 V 2.200 V 2.329 V V AD_BID max V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V 1.430 V 1.667 V 1.881 V 2.046 V 2.215 V 2.343 V BOARD ID Table Board ID PCB Revision EVT DVT PVT Pre-MP & MP 43 level BOM table 43 Level Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF D Description BOM Structure 4319TDBOL01 SMT MB AB511 Z5W1M UMA 2.17G N3520@/EMC@/AMIC@/EDP@/DBG@/TPM@/PCB@/TS@ 4319TDBOL02 SMT MB AB511 Z5W1M UMA 1.86G N2920@/EMC@/AMIC@/LVDS@/DBG@/TPM@/PCB@/TS@ 4319TDBOL03 SMT MB AB511 Z5W1M UMA 1.86G EPD HDMI N2920@/EMC@/AMIC@/EDP@/DBG@/TPM@/PCB@/TS@ 4319TDBOL04 4319TDBOL05 SMT MB AB511 Z5W1M UMA 2.17G LVDS HDMI N3520@/EMC@/AMIC@/LVDS@/DBG@/TPM@/PCB@/TS@ SMT MB AB511 Z5W1M UMA 2.13G EPD HDMI N2820@/EMC@/AMIC@/EDP@/DBG@/TPM@/PCB@/TS@ 4319TDBOL06 SMT MB AB511 Z5W1M UMA 2.13G LVDS HDMI N2820@/EMC@/AMIC@/LVDS@/DBG@/TPM@/PCB@/TS@ 435MNVBOL01 SMT IO/B SB471 Z5W1M EMC@ BOM Option Table Item CPU for N2920 pop CPU for N3520 pop TPM support No supoort TPM PCB PN CLEAN CMOS JUMP Touch Screen function EDP + Touch Screen BOM Structure N2920@ N3520@ TPM@ NTPM@ PCB@ SP@ TS@ ETS@ 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: A B C D Thursday, March 13, 2014 Sheet E of 39 A B C D 2.2K 2.2K BG25 SOC_I2C2_DATA BJ25 SOC_I2C2_CLK E 4.7K +1.8VS 4.7K +3V_TP I2C2_SDA_TP DMN63D8LDW Touch Pad I2C2_SCL_TP Dual channel NMOS 2.2K 2.2K SOC BH28 SOC_I2C5_DATA BG28 SOC_I2C5_CLK 2.2K +1.8VS 2.2K +5VS_TS I2C5_SDA_PNL DMN63D8LDW I2C5_SCL_PNL Touch Panel Dual channel NMOS 2.2K 2.2K BH10 PCU_SMB_CLK BG12 PCU_SMB_DATA +1.8VS DMN63D8LDW Dual channel NMOS 2.2K 2.2K 77 EC_SMB_CK1 78 EC_SMB_DA1 SCL1 SDA1 +3VALW_EC 100 ohm 100 ohm BATTERY CONN 2.2K 2.2K 79 SCL2 KBC 80 SDA2 +3VS EC_SMB_CK2 EC_SMB_DA2 3 200 202 KB9022 DIMMA SMBUS Address [A0h] 30 32 WLAN SMBUS Address [TBD] 4.7K 4.7K 85 SCL3 86 SDA3 +3VS_TL EC_SMB_CK3 10 EC_SMB_DA3 DP-LVDS SMBUS Address [TBD] 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SMB/I2C Rev 1.0 Bay Trail M LA-B511P Date: A B C D Thursday, March 13, 2014 Sheet E of 39 A B C D E 1 12000mA VR_ON ADAPTER ISL95833HRTZ-T (PU801) 14000mA SPOK SY8208DQNC (PU601) 325mA SYSON RT8207MZQW (PU501) 5250mA +SOC_VNN +SOC_VCC +1.0VALWP +1.35VP 2750mA SUSP ME4856-G (U25) SUSP# TPS22966DPUR (U26) +1.0VS 420mA +1.35VS +0.675VSP 2 BATTERY B+ EC_ON SY8208BQNC (PU401) 4850mA +3VALWP CHARGER SUSP# SY8003DFC_DFN8 (PU701) 458mA SUSP# APL5930KAI-TRG (PU602) 1000mA SPOK APL5930KAI-TRG (PU702) 110mA SUSP# TPS22966DPUR (U24) LAN_PWR_EN +1.5VSP +1.05VSP +1.8VALWP +3V_LAN 10mA TPS22966DPUR (U26) 1000mA +3VS G5243AT11U (U67) SUSP# ENVDD +1.8VS +3VS_WLAN G5243AT11U (U8) +LCDVDD 3 EC_ON SY8208BQNC (PU402) 10050mA SUSP# +5VALWP TPS22966DPUR (U24) 1000mA 1050mA +5VS +VDDA 1500mA +5VS_HDD 1500mA +5VS_ODD 500mA +HDMI_5V_OUT USB_PWR_EN# SY6288D10CAC (U17) 1500mA +USB3_VCCA 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title Power Rail THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: A B C D Thursday, March 13, 2014 Sheet E of 39 DDR_A_D[0 63] DDR_A_DQS[0 7] DDR_A_DQS#[0 7] USOC1A DDR_A_MA[0 15] D C DDR_A_DM[0 7] DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_CS0# DDR_A_CS2# DDR_A_CKE0 DDR_A_CKE2 DDR_A_ODT0 DDR_A_ODT2 DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK2 DDR_A_CLK2# DDR_A_RST# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 R1 R2 DRAM0_DQ_0 DRAM0_DQ_1 DRAM0_DQ_2 DRAM0_DQ_3 DRAM0_DQ_4 DRAM0_DQ_5 DRAM0_DQ_6 DRAM0_DQ_7 DRAM0_DQ_8 DRAM0_DQ_9 DRAM0_DQ_10 DRAM0_DQ_11 DRAM0_DQ_12 DRAM0_DQ_13 DRAM0_DQ_14 DRAM0_DQ_15 DRAM0_DQ_16 DRAM0_DQ_17 DRAM0_DQ_18 DRAM0_DQ_19 DRAM0_DQ_20 DRAM0_DQ_21 DRAM0_DQ_22 DRAM0_DQ_23 DRAM0_DQ_24 DRAM0_DQ_25 DRAM0_DQ_26 DRAM0_DQ_27 DRAM0_DQ_28 DRAM0_DQ_29 DRAM0_DQ_30 DRAM0_DQ_31 DRAM0_DQ_32 DRAM0_DQ_33 DRAM0_DQ_34 DRAM0_DQ_35 DRAM0_DQ_36 DRAM0_DQ_37 DRAM0_DQ_38 DRAM0_DQ_39 DRAM0_DQ_40 DRAM0_DQ_41 DRAM0_DQ_42 DRAM0_DQ_43 DRAM0_DQ_44 DRAM0_DQ_45 DRAM0_DQ_46 DRAM0_DQ_47 DRAM0_DQ_48 DRAM0_DQ_49 DRAM0_DQ_50 DRAM0_DQ_51 DRAM0_DQ_52 DRAM0_DQ_53 DRAM0_DQ_54 DRAM0_DQ_55 DRAM0_DQ_56 DRAM0_DQ_57 DRAM0_DQ_58 DRAM0_DQ_59 DRAM0_DQ_60 DRAM0_DQ_61 DRAM0_DQ_62 DRAM0_DQ_63 DRAM0_DM_0 DRAM0_DM_1 DRAM0_DM_2 DRAM0_DM_3 DRAM0_DM_4 DRAM0_DM_5 DRAM0_DM_6 DRAM0_DM_7 M45 M44 H51 DRAM0_RAS# DRAM0_CAS# DRAM0_WE# K47 K44 D52 DRAM0_BS_0 DRAM0_BS_1 DRAM0_BS_2 P44 DRAM0_CS_0# P45 DRAM0_CS_2# C47 D48 F44 E46 DRAM0_CKE_0 RESERVED_D48 DRAM0_CKE_2 RESERVED_E46 T41 DRAM0_ODT_0 P42 DRAM0_ODT_2 M50 M48 DRAM0_CKP_0 DRAM0_CKN_0 P50 P48 DRAM0_CKP_2 DRAM0_CKN_2 P41 DRAM0_DRAMRST# AF44 DDR_TERMN0 DDR_TERMN1 USOC1B DRAM0_MA_0 DRAM0_MA_1 DRAM0_MA_2 DRAM0_MA_3 DRAM0_MA_4 DRAM0_MA_5 DRAM0_MA_6 DRAM0_MA_7 DRAM0_MA_8 DRAM0_MA_9 DRAM0_MA_10 DRAM0_MA_11 DRAM0_MA_12 DRAM0_MA_13 DRAM0_MA_14 DRAM0_MA_15 DDR_A_DM0 G36 DDR_A_DM1 B36 DDR_A_DM2 F38 DDR_A_DM3 B42 DDR_A_DM4 P51 DDR_A_DM5 V42 DDR_A_DM6 Y50 DDR_A_DM7 Y52 +DDR_SOC_VREF 100K_0402_5% 100K_0402_5% K45 H47 L41 H44 H50 G53 H49 D50 G52 E52 K48 E51 F47 J51 B49 B50 DRAM_VREF AF42 AH42 0.675V ICLK_DRAM_TERMN_AF42 ICLK_DRAM_TERMN_AH42 DRAM0_DQSP_0 DRAM0_DQSN_0 DRAM0_DQSP_1 DRAM0_DQSN_1 DRAM0_DQSP_2 DRAM0_DQSN_2 DRAM0_DQSP_3 DRAM0_DQSN_3 DRAM0_DQSP_4 DRAM0_DQSN_4 DRAM0_DQSP_5 DRAM0_DQSN_5 DRAM0_DQSP_6 DRAM0_DQSN_6 DRAM0_DQSP_7 DRAM0_DQSN_7 B AD42 AB42 DDR_PWROK DDR_CORE_PWROK 23.2_0402_1% 29.4_0402_1% 162_0402_1% R3 R4 R5 DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2 Follow CRB v2.0 DRAM_VDD_S4_PWROK DRAM_CORE_PWROK AD44 AF45 AD45 DRAM_RCOMP_0 DRAM_RCOMP_1 DRAM_RCOMP_2 AF40 AF41 AD40 AD41 DDR_CORE_PWROK EMC@ C1 0.01U_0402_16V7K RESERVED_AF40 RESERVED_AF41 RESERVED_AD40 RESERVED_AD41 M36 J36 P40 M40 P36 N36 K40 K42 B32 C32 C36 A37 C33 A33 C37 B38 F36 G38 F42 J42 G40 C38 G44 D42 A41 C41 A45 B46 C40 B40 B48 B47 K52 K51 T52 T51 L51 L53 R51 R53 T47 T45 Y40 V41 T48 T50 Y42 AB40 V45 V47 AD48 AD50 V48 V50 AB44 Y45 V52 W51 AC53 AC51 W53 Y51 AD52 AD51 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 J38 K38 C35 B34 D40 F40 B44 C43 N53 M52 T42 T44 Y47 Y48 AB52 AA51 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 AY45 BB47 AW41 BB44 BB50 BC53 BB49 BF50 BC52 BE52 AY48 BE51 BD47 BA51 BH49 BH50 BD38 BH36 BC36 BH42 AT51 AM42 AK50 AK52 AV45 AV44 BB51 AY47 AY44 BF52 AT44 AT45 BG47 BE46 BD44 BF48 AP41 AT42 AV50 AV48 AT50 AT48 AT41 DRAM1_MA_0 DRAM1_MA_1 DRAM1_MA_2 DRAM1_MA_3 DRAM1_MA_4 DRAM1_MA_5 DRAM1_MA_6 DRAM1_MA_7 DRAM1_MA_8 DRAM1_MA_9 DRAM1_MA_10 DRAM1_MA_11 DRAM1_MA_12 DRAM1_MA_13 DRAM1_MA_14 DRAM1_MA_15 DRAM1_DQ_0 DRAM1_DQ_1 DRAM1_DQ_2 DRAM1_DQ_3 DRAM1_DQ_4 DRAM1_DQ_5 DRAM1_DQ_6 DRAM1_DQ_7 DRAM1_DQ_8 DRAM1_DQ_9 DRAM1_DQ_10 DRAM1_DQ_11 DRAM1_DQ_12 DRAM1_DQ_13 DRAM1_DQ_14 DRAM1_DQ_15 DRAM1_DQ_16 DRAM1_DQ_17 DRAM1_DQ_18 DRAM1_DQ_19 DRAM1_DQ_20 DRAM1_DQ_21 DRAM1_DQ_22 DRAM1_DQ_23 DRAM1_DQ_24 DRAM1_DQ_25 DRAM1_DQ_26 DRAM1_DQ_27 DRAM1_DQ_28 DRAM1_DQ_29 DRAM1_DQ_30 DRAM1_DQ_31 DRAM1_DQ_32 DRAM1_DQ_33 DRAM1_DQ_34 DRAM1_DQ_35 DRAM1_DQ_36 DRAM1_DQ_37 DRAM1_DQ_38 DRAM1_DQ_39 DRAM1_DQ_40 DRAM1_DQ_41 DRAM1_DQ_42 DRAM1_DQ_43 DRAM1_DQ_44 DRAM1_DQ_45 DRAM1_DQ_46 DRAM1_DQ_47 DRAM1_DQ_48 DRAM1_DQ_49 DRAM1_DQ_50 DRAM1_DQ_51 DRAM1_DQ_52 DRAM1_DQ_53 DRAM1_DQ_54 DRAM1_DQ_55 DRAM1_DQ_56 DRAM1_DQ_57 DRAM1_DQ_58 DRAM1_DQ_59 DRAM1_DQ_60 DRAM1_DQ_61 DRAM1_DQ_62 DRAM1_DQ_63 DRAM1_DM_0 DRAM1_DM_1 DRAM1_DM_2 DRAM1_DM_3 DRAM1_DM_4 DRAM1_DM_5 DRAM1_DM_6 DRAM1_DM_7 DRAM1_RAS# DRAM1_CAS# DRAM1_WE# DRAM1_BS_0 DRAM1_BS_1 DRAM1_BS_2 DRAM1_CS_0# DRAM1_CS_2# DRAM1_CKE_0 RESERVED_BE46 DRAM1_CKE_2 RESERVED_BF48 DRAM1_ODT_0 DRAM1_ODT_2 DRAM1_CKP_0 DRAM1_CKN_0 DRAM1_CKP_2 DRAM1_CKN_2 DRAM1_DRAMRST# DRAM1_DQSP_0 DRAM1_DQSN_0 DRAM1_DQSP_1 DRAM1_DQSN_1 DRAM1_DQSP_2 DRAM1_DQSN_2 DRAM1_DQSP_3 DRAM1_DQSN_3 DRAM1_DQSP_4 DRAM1_DQSN_4 DRAM1_DQSP_5 DRAM1_DQSN_5 DRAM1_DQSP_6 DRAM1_DQSN_6 DRAM1_DQSP_7 DRAM1_DQSN_7 OF 13 BG38 BC40 BA42 BD42 BC38 BD36 BF42 BC44 BH32 BG32 BG36 BJ37 BG33 BJ33 BG37 BH38 AU36 AT36 AV40 AT40 BA36 AV36 AY42 AY40 BJ41 BG41 BJ45 BH46 BG40 BH40 BH48 BH47 AY52 AY51 AP52 AP51 AW51 AW53 AR51 AR53 AP47 AP45 AK40 AM41 AP48 AP50 AK42 AH40 AM45 AM47 AF48 AF50 AM48 AM50 AH44 AK45 AM52 AL51 AG53 AG51 AL53 AK51 AF52 AF51 D C BF40 BD40 BG35 BH34 BA38 AY38 BH44 BG43 AU53 AV52 AP42 AP44 AK47 AK48 AH52 AJ51 B OF 13 FH8065301546401_FCBGA131170 @ FH8065301546401_FCBGA131170 @ Close To SOC Pin USOC1 N3530@ +1.35V A USOC1 N2830@ USOC1 N2930@ +DDR_SOC_VREF 1 R6 4.7K_0402_1% R7 4.7K_0402_1% S IC FH8065301728500 QG9T C0 2.17G FCBGA Part Number = SA00007QQ70 S IC FH8065301729601 QG9V C0 2.17G ABO! Part Number = SA00007QR30 A S IC FH8065301729501 QG9U C0 1.83G FCBGA Part Number = SA00007RV70 C2 1U_0402_16V7K Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title VLV-M SOC Memory DDR3L THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: Thursday, March 13, 2014 Sheet of 39 D D USOC1C AL3 AL1 D27 HDMI_HPD# HDMI_DDCDATA HDMI_DDCCLK C26 C28 B28 C27 B26 R9 DDI0_RCOMPP 402_0402_1% DDI0_RCOMPN C Follow CRB v2.0 0ohm till to GND AK12 AK13 AM14 AM13 AM3 AM2 DDI0_TXP_0 DDI0_TXN_0 DDI0_TXP_1 DDI0_TXN_1 DDI0_TXP_2 DDI0_TXN_2 DDI0_TXP_3 DDI0_TXN_3 1.0V 1.0V DDI0_AUXP DDI0_AUXN DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3 1.0V 1.0V DDI1_AUXP DDI1_AUXN DDI1_HPD +1.8VS @ R10 10K_0402_5% B @ T1 GPIO_NC12 EDP_AUXP EDP_AUXN K30 1.8V 1.8V 1.8V 1.8V 1.8V DDI1_DDCDATA 1.8V DDI1_DDCCLK P30 DDI1_ENABLE R8 G30 1.8V 1.8V 1.8V N30 DDI1_ENVDD J30 DDI1_ENBKL M30 DDI1_PWM DDI0_VDDEN DDI0_BKLTEN DDI0_BKLTCTL DDI1_VDDEN DDI1_BKLTEN DDI1_BKLTCTL VSS_AH3 VSS_AH2 DDI0_RCOMP_P DDI0_RCOMP_N RESERVED_AM14 RESERVED_AM13 VSS_AM3 VSS_AM2 RESERVED_AH14 RESERVED_AH13 RESERVED_AF14 RESERVED_AF13 RESERVED_T2 RESERVED_T3 RESERVED_AB3 RESERVED_AB2 RESERVED_Y3 RESERVED_Y2 RESERVED_W3 RESERVED_W1 RESERVED_V2 RESERVED_V3 RESERVED_R3 RESERVED_R1 RESERVED_AD6 RESERVED_AD4 RESERVED_AB9 RESERVED_AB7 RESERVED_Y4 RESERVED_Y6 RESERVED_V4 RESERVED_V6 GPIO_S0_NC_13 GPIO_S0_NC14 RESERVED_AB14 GPIO_S0_NC_12 RESERVED_C30 3.3V 3.3V VGA_HSYNC VGA_VSYNC 3.3V 3.3V VGA_DDCCLK VGA_DDCDATA RESERVED_T7 RESERVED_T9 RESERVED_AB13 RESERVED_AB12 RESERVED_Y12 RESERVED_Y13 RESERVED_V10 RESERVED_V9 RESERVED_T12 RESERVED_T10 RESERVED_V14 RESERVED_V13 RESERVED_T14 RESERVED_T13 RESERVED_T6 RESERVED_T4 RESERVED_P14 GPIO_S0_NC_15 GPIO_S0_NC_16 GPIO_S0_NC_17 GPIO_S0_NC_18 GPIO_S0_NC_19 GPIO_S0_NC_20 GPIO_S0_NC_21 GPIO_S0_NC_22 GPIO_S0_NC_23 GPIO_S0_NC_24 GPIO_S0_NC_25 GPIO_S0_NC_26 Follow CRB v2.0 OF 10 FH8065301546401_FCBGA131170 EDP_HPD# 2.2K_0402_5% +1.8VS Follow CRB v2.0 0ohm till to GND AH14 AH13 AF14 AF13 C BA3 AY2 BA1 AW1 AY3 BD2 BF2 BC1 BC2 T7 T9 AB13 AB12 Y12 Y13 V10 V9 T12 T10 V14 V13 T14 T13 T6 T4 P14 F34 M32 D28 J28 K34 D34 F32 F28 K28 J34 N32 D32 B eDP +3VS DDI1_ENBKL 0_0402_5% R13 @ ENBKL Modify R02 +1.8VS @ From check list: GPIO_S0_NC[13] Multiplexed with Hardware AH3 AH2 eDP Panel AK3 AK2 DDI0_DDCDATA DDI0_DDCCLK @ T2 R11 10K_0402_1% GPIO_NC13 GPIO_NC14 EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 DDI0_HPD VGA_RED VGA_BLUE VGA_GREEN VGA_IREF VGA_IRTN T2 T3 AB3 AB2 Y3 Y2 W3 W1 V2 V3 R3 R1 AD6 AD4 AB9 AB7 Y4 Y6 V4 V6 A29 C29 AB14 B30 C30 AG3 AG1 AF3 AF2 AD3 AD2 AC3 AC1 Straps Pin:MDSI_DDCDATA Y A ENVDD RP1 P Y A INVT_PWM_SOC 2013/04/12 100K_0804_8P4R_5% NL17SZ07DFT2G_SC70-5 SA00004BV00 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date DDI1_ENBKL DDI1_ENVDD DDI1_PWM U3 NC 2 G DDI1_PWM INVT_PWM_SOC 4.7K_0402_5% R15 NL17SZ07DFT2G_SC70-5 SA00004BV00 +1.8VS A ENVDD 4.7K_0402_5% R14 U2 NC DDI1_ENVDD P HDMI AV3 AV2 AT2 AT3 AR3 AR1 AP3 AP2 HDMI_TX2+ HDMI_TX2HDMI_TX1+ HDMI_TX1HDMI_TX0+ HDMI_TX0HDMI_CLK+ HDMI_CLK- G 2014/04/12 Deciphered Date Title VLV-M SOC Display THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: Thursday, March 13, 2014 Sheet of 39 A D D USOC1D HDD ODD SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 BF6 BG7 AU16 AV16 BD10 BF10 AY16 BA16 Follow CRB V2.0 0ohm till to GND SOC_SCI# @ T3 Modify R02 C SOC_SCI# DEVSLP_SOC BB10 BC10 BA12 AY14 AY12 R16 SATA_RCOMPP AU18 402_0402_1% SATA_RCOMPN AT18 AT22 AV20 AU22 AV22 AT20 AY24 AU26 AT26 AU20 AV26 BA24 AY18 BA18 AY20 BD20 BA20 BD18 BC18 AY26 AT28 BD26 AU28 BA26 BC24 AV28 BF22 BD22 B BF26 SATA_TXP_0 SATA_TXN_0 PCIE_TXP_0 PCIE_TXN_0 SATA_RXP_0 SATA_RXN_0 PCIE_RXP_0 PCIE_RXN_0 SATA_TXP_1 SATA_TXN_1 PCIE_TXP_1 PCIE_TXN_1 SATA_RXP_1 SATA_RXN_1 PCIE_RXP_1 PCIE_RXN_1 VSS_BB10 VSS_BC10 PCIE_TXP_2 PCIE_TXN_2 SATA_GP0 / GPIO_S0_SC_0 SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1 SATA_LED# / GPIO_S0_SC_2 PCIE_RXP_2 PCIE_RXN_2 PCIE_TXP_3 PCIE_TXN_3 SATA_RCOMP_P SATA_RCOMP_N PCIE_RXP_3 PCIE_RXN_3 MMC1_CLK / GPIO_S0_SC_16 VSS_BB7 VSS_BB5 MMC1_D0 / GPIO_S0_SC_17 MMC1_D1 / GPIO_S0_SC_18 MMC1_D2 / GPIO_S0_SC_19 MMC1_D3 / GPIO_S0_SC_20 MMC1_D4 / GPIO_S0_SC_21 MMC1_D5 / GPIO_S0_SC_22 MMC1_D6 / GPIO_S0_SC_23 MMC1_D7 / GPIO_S0_SC_24 PCIE_CLKREQ_0# / GPIO_S0_SC_3 PCIE_CLKREQ_1# / GPIO_S0_SC_4 PCIE_CLKREQ_2# / GPIO_S0_SC_5 PCIE_CLKREQ_3# / GPIO_S0_SC_6 SD3_WP / GPIO_S0_SC_7 MMC1_CMD / GPIO_S0_SC_25 MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26 PCIE_RCOMP_P PCIE_RCOMP_N RESERVED_BB4 RESERVED_BB3 MMC1_RCOMP SD2_CLK / GPIO_S0_SC_27 SD2_D0 / GPIO_S0_SC_28 SD2_D1 / GPIO_S0_SC_29 SD2_D2 / GPIO_S0_SC_30 SD2_D3_CD# / GPIO_S0_SC_31 SD2_CMD / GPIO_S0_SC_32 RESERVED_AV10 RESERVED_AV9 HDA_LPE_RCOMP HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8 HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9 HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10 HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11 HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12 HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13 SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14 SD3_D0 / GPIO_S0_SC_34 HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15 SD3_D1 / GPIO_S0_SC_35 SD3_D2 / GPIO_S0_SC_36 LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62 SD3_D3 / GPIO_S0_SC_37 LPE_I2S2_FRM / GPIO_S0_SC_63 SD3_CD# / GPIO_S0_SC_38 LPE_I2S2_DATAIN / GPIO_S0_SC_64 SD3_CMD / GPIO_S0_SC_39 LPE_I2S2_DATAOUT / GPIO_S0_SC_65 SD3_1P8EN / GPIO_S0_SC_40 SD3_PWREN# / GPIO_S0_SC_41 RESERVED_P34 RESERVED_N34 SD3_RCOMP RESERVED_AK9 RESERVED_AK7 OF 10 FH8065301546401_FCBGA131170 PROCHOT# AY7 PCIE_PTX_DRX_P0 AY6 PCIE_PTX_DRX_N0 1U_0402_16V7K 1U_0402_16V7K C5 C3 AT14 PCIE_PRX_DTX_P0 AT13 PCIE_PRX_DTX_N0 PCIE_PTX_C_DRX_P0 PCIE_PTX_C_DRX_N0 PCIE LAN PCIE_PRX_DTX_P0 PCIE_PRX_DTX_N0 AV6 PCIE_PTX_DRX_P1 AV4 PCIE_PTX_DRX_N1 1U_0402_16V7K 1U_0402_16V7K C4 C6 AT10 PCIE_PRX_DTX_P1 AT9 PCIE_PRX_DTX_N1 PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1 WLAN PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 AT7 AT6 AP12 AP10 AP6 AP4 C +1.8VS AP9 AP7 RP2 BB7 BB5 BG3 BD7 BG5 BE3 BD5 LAN_CLKREQ# WLAN_CLKREQ# PCIE_CLKREQ_2# PCIE_CLKREQ_3# AP14 AP13 PCIE_RCOMPP PCIE_RCOMPN LAN_CLKREQ# PCIE_CLKREQ_2# PCIE_CLKREQ_3# WLAN_CLKREQ# Follow CRB V2.0 0ohm till to GND LAN_CLKREQ# WLAN_CLKREQ# 10K_0804_8P4R_5% RP3 HDA_SYNC HDA_SDOUT HDA_BIT_CLK HDA_RST# R17 402_0402_1% BB4 BB3 HDA_SYNC_AUDIO HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO HDA_RST_AUDIO# 33_0804_8P4R_5% EMC@ AV10 AV9 HDA_RCOMP BF20 BG22 BH20 BJ21 BG20 BG19 BG21 BH18 BG18 BF28 BA30 BD28 BC30 HDA_RCOMP HDA_RST# HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDIN0 T4 T5 T6 R18 HDA_BITCLK_AUDIOC7 49.9_0402_1% 22P_0402_50V8J @EMC@ @ @ @ HDA_SDIN0 GPIO_S0_SC_65 Follow CRB v2.0 P34 N34 R20 73.2_0402_1% AK9 AK7 C24 2 GPIO_S0_SC_63 R19 +1.8VS 10K_0402_5% +1.0VS H_PROCHOT# Internal PD 2K @ B GPIO_S0_SC_63: BIOS/EFI Boot Strap (BBS) = LPC = SPI GPIO_S0_SC_63 GPIO_S0_SC_65: Security Flash Descriptors = Override = Normal Operation (Internal PU) @EMC@ C8 10P_0402_50V8J +1.8VS EC programing : "High"for Flash BIOS R21 10K_0402_5% GPIO_S0_SC_65 D A S Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 A TXE_DBG G Q1 MESS138W-G_SOT323-3 2014/04/12 Deciphered Date Title VLV-M SOC SATA/PCI-E/HDA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: Thursday, March 13, 2014 Sheet of 39 +3VS 1 AD10 AD12 C9 10P_0402_25V8J 4.02K_0402_1% ICLK_ICOMP 47.5_0402_1% ICLK_RCOMP LAN CLK_PCIE_LAN# CLK_PCIE_LAN WLAN CLK_PCIE_WLAN# CLK_PCIE_WLAN RESERVED_AD10 RESERVED_AD12 AF6 AF4 PCIE_CLKN_0 PCIE_CLKP_0 AF9 AF7 PCIE_CLKN_2 PCIE_CLKP_2 AM4 AM6 R03 modify 1 R27 R28 R29 @ @ 51_0402_5% XDP_H_PRDY# 51_0402_5% XDP_H_TDO 200_0402_5% XDP_H_PREQ_BUF# RESERVED_AM9 RESERVED_AM10 BH7 BH5 BH4 BH8 BH6 BJ9 RP5 @ PCIE_CLKN_3 PCIE_CLKP_3 AM9 AM10 For XDP use XDP_H_TDI XDP_H_TMS XDP_H_TCK XDP_H_TRST# PMC_PLT_CLK_0 / GPIO_S0_SC_96 PMC_PLT_CLK_1 / GPIO_S0_SC_97 PMC_PLT_CLK_2 / GPIO_S0_SC_98 PMC_PLT_CLK_3 / GPIO_S0_SC_99 PMC_PLT_CLK_4 / GPIO_S0_SC_100 PMC_PLT_CLK_5 / GPIO_S0_SC_101 D14 XDP_H_TCK G12 XDP_H_TRST# F14 XDP_H_TMS F12 XDP_H_TDI G16 XDP_H_TDO D18 XDP_H_PRDY# XDP_H_PREQ_BUF# F16 AT34 51_0804_8P4R_5% C @ T10 SOC_SPI_MISO SOC_SPI_MOSI SOC_SPI_CLK TS_INT_R# PCH_TP_INT# 1 0_0402_5% 0_0402_5% SOC_LID_OUT# SOC_SMI# ILB_RTC_X1 ILB_RTC_X2 ILB_RTC_EXTPAD RTC_VCC_P22 SVID_ALERT# SVID_DATA SVID_CLK SIO_PWM_0 / GPIO_S0_SC_94 SIO_PWM_1 / GPIO_S0_SC_95 GPIO_S5_8 GPIO_S5_9 GPIO_S5_10 N26 D26 G24 F18 F22 D22 J20 D20 F26 K26 J26 BG9 F20 J24 G18 P 3.3V PLT_RST_BUF# NL17SZ07DFT2G_SC70-5 SA00004BV00 PLT_RST_BUF# PLT_RST Buffer C10 @EMC@ 0.01U_0402_16V7K D +1.8VALW PMC_SUSCLK @ 32.768k T7 PMC_SLP_S4# PMC_SLP_S3# GPIO_S5_14 PMC_ACIN PMC_PCIE_WAKE# PMC_BATLOW# PMC_PWRBTN# PMC_RSTBTN# PMC_PLTRST# GPIO_S5_17 output RP4 PMC_PCIE_WAKE# PMC_BATLOW# GPIO_S5_14 10K_0804_8P4R_5% T8 @ T9 @ PMC_CORE_PWROK C12 EMC@ 0.01U_0402_16V7K DDR_CORE_PWROK C13 EMC@ 0.01U_0402_16V7K PMC_PLTRST# C14 EMC@ 1U_0402_16V7K C11 RTC_TEST# C12 RTC_RST# EC_RSMRST# B10 B7 EC_RSMRST# PMC_CORE_PWROK C9 A9 B8 P22 ILB_RTC_X1 ILB_RTC_X2 ILB_RTC_EXTPAD EC_RSMRST# +RTCVCC R30 100K_0402_5% EMC@ 1U_0402_16V7K C15 C16 1U_0402_16V7K B24 VR_SVID_ALERT#_SOC R32 A25 VR_SVID_DATA_SOC R33 C25 1 +1.35VS R31 73.2_0402_1% 20_0402_1% 16.9_0402_1% +3VALW VR_SVID_ALERT# VR_SVID_DATA VR_SVID_CLK AU32 AT32 K24 N24 M20 J18 M18 K18 K20 M22 M24 3.3V PMC_CORE_PWROK R35 10M_0402_5% U6 1.35V Y A C R38 10K_0402_5% NC DDR_CORE_PWROK NL17SZ07DFT2G_SC70-5 SA00004BV00 GPIO_RCOMP SIO_SPI_CS# / GPIO_S0_SC_66 SIO_SPI_MISO / GPIO_S0_SC_67 SIO_SPI_MOSI / GPIO_S0_SC_68 SIO_SPI_CLK / GPIO_S0_SC_69 OF 13 RP6 PMC_SLP_S4# SOC_KBRST# SOC_LID_OUT# 32.768KHZ_12.5PF_Q13FC135000040 Y2 EC_SLP_S4# EC_KBRST# EC_LID_OUT# EC_SLP_S4# EC_KBRST# EC_LID_OUT# 0_0804_8P4R_5% FH8065301546401_FCBGA131170 AV32 BA28 AY28 AY30 C17 18P_0402_50V8J RP7 SOC_SMI# SOC_SCI# PMC_PWRBTN# C18 18P_0402_50V8J SOC_SCI# Modify R03 EC_SMI# EC_SCI# PBTN_OUT# EC_SMI# EC_SCI# PBTN_OUT# 0_0804_8P4R_5% R213 0_0402_5% SOC_SERIRQ NTPM@ NTPM@ PMC_SLP_S3# R214 0_0402_5% @ R37 49.9_0402_1% ACIN BF34 BD34 BD32 BF32 Y A ILB_RTC_X1 ILB_RTC_X2 GPIO_S5_22 GPIO_S5_23 GPIO_S5_24 GPIO_S5_25 GPIO_S5_26 GPIO_S5_27 GPIO_S5_28 GPIO_S5_29 GPIO_S5_30 GPIO_RCOMP RB751V40_SC76-2 PMC_PLTRST# +1.0VS RTC domain GPIO_S5_0 GPIO_S5_1 / PMC_WAKE_PCIE_1 GPIO_S5_2 / PMC_WAKE_PCIE_2 GPIO_S5_3 / PMC_WAKE_PCIE_3 GPIO_S5_4 GPIO_S5_5 / PMU_SUSCLK_1 GPIO_S5_6 / PMU_SUSCLK_2 GPIO_S5_7 / PMU_SUSCLK_3 C13 A13 C19 B PMC_RSMRST# PMC_CORE_PWROK PCU_SPI_CS_0# PCU_SPI_CS_1# / GPIO_S5_21 PCU_SPI_MISO PCU_SPI_MOSI PCU_SPI_CLK B18 B16 C18 A17 C17 C16 B14 C15 SOC_KBRST# SOC_TS_INT# SOC_TP_INT# 2R34 R36 modify R02 @ @ ILB_RTC_TEST# ILB_RTC_RST# TAP_TCK TAP_TRST# TAP_TMS TAP_TDI TAP_TDO TAP_PRDY# TAP_PREQ# RESERVED_AT34 C23 C21 B22 A21 C22 SOC_SPI_CS0# PMC_SUSPWRDNACK / GPIO_S5_11 PMC_SUSCLK_0 / GPIO_S5_12 PMC_SLP_S0IX# / GPIO_S5_13 PMC_SLP_S4# PMC_SLP_S3# GPIO_S5_14 PMC_ACPRESENT PMC_WAKE_PCIE_0# / GPIO_S5_15 PMC_BATLOW# PMC_PWRBTN# / GPIO_S5_16 PMC_RSTBTN# PMC_PLTRST# GPIO_S5_17 PMC_SUS_STAT# / GPIO_S5_18 PCIE_CLKN_1 PCIE_CLKP_1 AK4 AK6 +1.8VALW SIO_UART2_RXD / GPIO_S0_SC_74 SIO_UART2_TXD / GPIO_S0_SC_75 SIO_UART2_RTS# / GPIO_S0_SC_76 SIO_UART2_CTS# / GPIO_S0_SC_77 +1.8VALW R25 R26 ICLK_ICOMP ICLK_RCOMP D1 2.2K_0402_5% 2 RESERVED_AD9 AD14 AD13 ICLK_ICOMP ICLK_RCOMP PMC_ACIN XTAL_25M_OUT R24 P AU34 AV34 BA34 AY34 G GND AD9 SIO_UART1_RXD / GPIO_S0_SC_70 SIO_UART1_TXD / GPIO_S0_SC_71 SIO_UART1_RTS# / GPIO_S0_SC_72 SIO_UART1_CTS# / GPIO_S0_SC_73 3 GND ICLK_OSCIN ICLK_OSCOUT R22 4.7K_0402_5% U4 NC 1 C11 10P_0402_25V8J D 1 AH12 XTAL_25M_IN XTAL_25M_OUT AH10 R23 1M_0402_5% Y1 25MHZ_10PF_7V25000014 1.8V USOC1E G XTAL_25M_IN +1.8VS +1.8VALW EC_SERIRQ PMC_SLP_S3# R116 B 2.2K_0402_5% TPM@ EC_SLP_S3# +1.8VALW +3VALW_EC +1.8VALW U27 +BIOS_SPI C19 RTC_TEST# RTC_RST# SPI ROM ( 8MByte ) 1.8V SPI_CS0# SPI_CLK SPI_MOSI SPI_MISO CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0) SOC_SPI_CLK SOC_SPI_MOSI SOC_SPI_MISO SOC_SPI_CS0# SPI_CLK SPI_MOSI SPI_MISO SPI_CS0# 22_0804_8P4R_5% EMC@ Q21 TPM@ MESS138W-G_SOT323-3 trace width 10mil +RTCBATT RTC_TEST# EC_SLP_S3# Modify R02 W25Q64DWSSIG_SO8 CL_CMOS @ S SP@ JCMOS1 SHORT PADS SP@ JCMOS2 SHORT PADS @EMC@ C23 10P_0402_50V8J +RTCVCC Clear CMOS Close to RAM door 1 Modify R03 A C22 1U_0402_16V7K BAS40-04_SOT23-3 Reserve for EMI(Near SPI ROM) @EMC@ R47 33_0402_5% +RTCVCC D G Q19 MESS138W-G_SOT323-3 SPI_CLK W=20mils +CHGRTC Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title VLV-M SOC CLK/PMU/SPI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: D2 PMC_SLP_S3# W=20mils SPI_HOLD# SPI_CLK SPI_MOSI RP9 From CPU EC_SERIRQ U7 SPI_CS0# SPI_MISO SPI_WP# 22_0804_8P4R_5% EMC@ A 20K_0402_1% C21 1U_0402_6.3V6K +BIOS_SPI RP8 EC_SPICS# EC_SPICLK EC_MOSI EC_MISO R44 D From EC (For share ROM) S C20 1U_0402_6.3V6K SPI_HOLD# VCCB EO B4 G2129TL1U_SC70-6 TPM@ +1.8VALW R42 20K_0402_1% 1 SPI_WP# 3.3K_0402_5% 0_0402_5% 1U_0402_16V7K 2 3.3K_0402_5% @ VCCA GND A4 G R43 R40 SOC_SERIRQ +1.8VALW Modify R03 SPI_CS0# 3.3K_0402_5% R41 EC_SPICS# EC_SPICLK EC_MOSI EC_MISO +RTCVCC +BIOS_SPI R39 SOC_SERIRQ Thursday, March 13, 2014 Sheet of 39 USOC1F M3 L1 K2 K3 M2 N3 P2 L3 J3 P3 H3 B12 USB20_P0 USB20_N0 USB Hub USB20_P1 USB20_N1 Touch Panel USB20_P2 USB20_N2 USB3.0 Connector Camera +1.8VALW R49 R51 C 1 10K_0402_5% USB_OC0# 10K_0402_5% USB_OC1# M16 K16 J14 G14 K12 J12 K10 H10 USB20_P3 USB20_N3 1 1K_0402_1% 1K_0402_1% USB_OC0# ICLK_USB_TERMP ICLK_USB_TERMN USB_OC1# D10 F10 C20 B20 GPIO_S5_32 GPIO_S5_33 GPIO_S5_34 GPIO_S5_35 GPIO_S5_36 GPIO_S5_37 GPIO_S5_38 GPIO_S5_39 RESERVED_P6 RESERVED_P7 RESERVED_M7 USB3_REXT0 RESERVED_P10 RESERVED_P12 RESERVED_M4 RESERVED_M6 GPIO_S5_40 GPIO_S5_41 GPIO_S5_42 GPIO_S5_43 USB3_RXP0 USB3_RXN0 USB3_TXP0 USB3_TXN0 USB_DP0 USB_DN0 BIOS/EFI Top Swap M10 M9 While updating the BIOS/EFI boot sector in flash, unexpected system power loss can cause an incomplete write resulting in a corrupt boot sector P6 P7 R48 M7 1.24K_0402_1% M12 USB3_REXT0 D Reference EDS v1.5 Page2294 P10 P12 M4 M6 D4 E3 PCH_USB3_RX0_P PCH_USB3_RX0_N K6 K7 PCH_USB3_TX0_P PCH_USB3_TX0_N USB3 Port USB_DP1 USB_DN1 USB_DP2 USB_DN2 BIOS/EFI Top Swap USB_DP3 USB_DN3 RESERVED_H8 RESERVED_H7 ICLK_USB_TERMP ICLK_USB_TERMN RESERVED_H4 RESERVED_H5 H8 H7 +1.8VS H4 H5 Modify R02 C R53 10K_0402_5% USB_OC_0# / GPIO_S5_19 USB_OC_1# / GPIO_S5_20 GPIO_S0_SC_56 R50 R52 RESERVED_M10 RESERVED_M9 D GPIO_S5_31 G2 NOTE: Ref checklist rev1.2 p.24 USB_PLL_MON is a single ended signal and should follow single ended signal routing requirements B4 B5 NOTE: Ref checklist rev1.2 p.25 USB_HSIC_RCOMP must NOT float if they are not being used +1.8VS HSIC_RCOMP 45.3_0402_1% R57 E2 D2 A7 USB_PLL_MON USB_HSIC0_DATA USB_HSIC0_STROBE ILB_8254_SPKR / GPIO_S0_SC_54 49.9_0402_1%1 2.2K_0804_8P4R_5% EMC@ R02 modify +1.8VS LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_CLK_EC CLK_PCI_TPM LPC_CLKRUN# SOC_SERIRQ R58 SIO_I2C0_DATA / GPIO_S0_SC_78 SIO_I2C0_CLK / GPIO_S0_SC_79 LPC_CLK_0 22_0402_5% EMC@ R61 LPC_CLK_1 22_0402_5% EMC@ R62 LPC_CLKRUN# BF18 BH16 BJ17 BJ13 BG14 BG17 BG15 BH14 BG16 BG13 SIO_I2C1_DATA / GPIO_S0_SC_80 SIO_I2C1_CLK / GPIO_S0_SC_81 LPC_RCOMP / VGA_RCOMP ILB_LPC_AD_0 / GPIO_S0_SC_42 ILB_LPC_AD_1 / GPIO_S0_SC_43 ILB_LPC_AD_2 / GPIO_S0_SC_44 ILB_LPC_AD_3 / GPIO_S0_SC_45 ILB_LPC_FRAME# / GPIO_S0_SC_46 ILB_LPC_CLK_0 / GPIO_S0_SC_47 ILB_LPC_CLK_1 / GPIO_S0_SC_48 ILB_LPC_CLKRUN# / GPIO_S0_SC_49 ILB_LPC_SERIRQ / GPIO_S0_SC_50 S D PCU_SMB_CLK Q4A DMN63D8LDW_SOT363-6 SIO_I2C3_DATA / GPIO_S0_SC_84 SIO_I2C3_CLK / GPIO_S0_SC_85 SIO_I2C5_DATA / GPIO_S0_SC_88 SIO_I2C5_CLK / GPIO_S0_SC_89 ILB_LPC_CLK_0 : Output Need Check with EC Q4B DMN63D8LDW_SOT363-6 of 25MHz, OF 13 ILB_LPC_CLK_1 is for CLK_0 feedback.(Input) Set to Outpot for Normal Usage * 1: DISABLED 0: ENABLED BH22 BG23 For Touch Screen BG24 BH24 BG25 BJ25 SOC_I2C2_DATA SOC_I2C2_CLK SOC_I2C5_DATA R59 SOC_I2C5_CLK R60 +1.8VS EDP@ 2.2K_0402_5% EDP@2 2.2K_0402_5% B BG26 BH26 BF27 BG27 BH28 BG28 SOC_I2C5_DATA EDP@ Q2A DMN63D8LDW_SOT363-6 SOC_I2C5_DATA SOC_I2C5_CLK SOC_I2C5_CLK Modify R02 SIO_I2C6_DATA / GPIO_S0_SC_90 SIO_I2C6_CLK / GPIO_S0_SC_91 / SD3_WP PCU_SMB_DATA S D EC_SMB_DA2 +1.8VS PCU_SMB_DATA / GPIO_S0_SC_51 PCU_SMB_CLK / GPIO_S0_SC_52 PCU_SMB_ALERT# / GPIO_S0_SC_53 G SIO_I2C2_DATA / GPIO_S0_SC_82 SIO_I2C2_CLK / GPIO_S0_SC_83 BG12 PCU_SMB_DATA BH10 PCU_SMB_CLK PCU_SMB_ALERT# BG11 G EC_SMB_CK2 SOC_SPKR USB_HSIC_RCOMP SIO_I2C4_DATA / GPIO_S0_SC_86 SIO_I2C4_CLK / GPIO_S0_SC_87 Pull High at EC side LPC_RCOMP SOC_SPKR B PCU_SMB_CLK PCU_SMB_DATA PCU_SMB_ALERT# BIOS/EFI Top Swap BH12 GPIO_S0_SC_56 USB_HSIC1_DATA USB_HSIC1_STROBE RP10 R55 @ 10K_0402_5% GPIO_S0_SC_56 FH8065301546401_FCBGA131170 GPIO_S0_SC_092 GPIO_S0_SC_093 I2C5_SDA_PNL I2C5_SCL_PNL M13 BD12 BC12 BD14 BC14 BF14 BD16 BC16 G USB_PLL_MON GPIO_S0_SC_55 GPIO_S0_SC_56 GPIO_S0_SC_57 / PCU_UART_TXD GPIO_S0_SC_58 GPIO_S0_SC_59 GPIO_S0_SC_60 GPIO_S0_SC_61 / PCU_UART_RXD EDP@ Q2B DMN63D8LDW_SOT363-6 D USB_RCOMPO USB_RCOMPI S R56 @ 0_0402_5% D6 C7 USB_RCOMP G D R54 45.3_0402_1% S C24 @EMC@ 10P_0402_50V8J LPC_CLK_0 BJ29 BG29 BH30 BG30 GPIO_S0_SC_92 GPIO_S0_SC_93 T14 @ T15 @ For Touch Pad +1.8VS @ SOC_I2C2_DATA R63 SOC_I2C2_CLK 2.2K_0402_5% PDA (Platform Debug Assistant) Test Points R64 +3VS 2.2K_0402_5% +1.8VS CPU Thermal sensor SDATA D+ ALERT# D- GND THERM# REMOTE1+ REMOTE1- THERM# @ R258 10K_0402_5% G @ C276 2200P_0402_50V7K +3VS REMOTE1- ADM1032ARMZ-2REEL_MSOP8 Modify R03 B C @ Q22 MMST3904-7-F_SOT323-3 I2C2_SDA_TP I2C2_SCL_TP D SOC_I2C2_DATA Q3A DMN63D8LDW_SOT363-6 REMOTE1+ G 2 S SOC_I2C2_CLK Modify R02 E Q3B DMN63D8LDW_SOT363-6 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 D VDD S SCLK 1 EC_SMB_DA2 @ EC_SMB_CK2 0.1U_0402_16V4Z C275 A @ U28 2014/04/12 Deciphered Date Title VLV-M SOC USB/LPC/SMBus THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: Thursday, March 13, 2014 Sheet 10 of 39 A A B C D VIH=1.2~5.5V 3.3V@100k/0.1uF=3.538ms 3.3V@120k/0.1uF=4.272ms SUSP# +1.0VALW TO +1.0VS 0708:Change to SB00000PZ00 / need apply footprint +1.0VALW U25 ME4856_SO8 5VS_ON +5VALW ON1 VBIAS VOUT1 VOUT1 CT1 GND ON2 CT2 VIN2 VIN2 VOUT2 VOUT2 GPAD 14 13 +3VS_OUT 12 C260 330P_0402_50V7K +3VS JUMP_43X118 11 10 330P_0402_50V7K C262 +5VS_OUT 15 JP7 JP@ +5VS JUMP_43X118 VIH=1.2~5.5V 3.3V@82k/0.1uF=3.042ms 3.3V@47k/0.1uF=1.893ms +1.0VS_R 1.8VS_ON SUSP G Q14 @ 2N7002K_SOT23-3 S U26 +1.8VALW R243 82K_0402_5% SUSP# D C268 1U_0402_16V7K C267 1U_0402_16V7K R244 47K_0402_5% C270 1U_0402_16V7K 0701 update S +5VALW VIN1 VIN1 Modify R02 1 D G Q15 2N7002K_SOT23-3 1.0VS_GATE 3VS_ON Rise Time: 3.3V@330pF = 889.68us 5.0V@330pF = 1348us APE8990GN3B DFN 14P DUAL LOAD SW Modify R03 SUSP +3VALW JP6 JP@ C265 4.7U_0603_6.3V6K @ R241 470_0603_5% R242 1K_0402_5% 2 +5VALW +1.0VS C264 4.7U_0603_6.3V6K 0701 update U24 R239 100K_0402_5% C261 1U_0402_16V7K R240 120K_0402_5% C263 1U_0402_16V7K E Modify R03 +5VALW 1.35VS_ON +1.35V JP8 JP@ VIN1 VIN1 VOUT1 VOUT1 ON1 CT1 VBIAS GND ON2 CT2 VIN2 VIN2 VOUT2 VOUT2 GPAD 14 13 +1.8VS_OUT 12 C266 330P_0402_50V7K +1.8VS Rise Time: 1.8V@330pF = 485.28us 1.35V@330pF = 363.96us JUMP_43X79 11 10 330P_0402_50V7K C269 +1.35VS_OUT 15 JP9 JP@ +1.35VS JUMP_43X79 APE8990GN3B DFN 14P DUAL LOAD SW Modify R02 Reset Button / Battery discharge screw hole Follow VA52_HB design SW3 Reset Button BI_GATE BI_GATE +5VALW SKPMAME010_2P R245 100K_0402_5% +3VLP SUSP SUSP D R247 10K_0402_5% SUSP# EC_RST# G G S G BI_GATE D BI_GATE PH to +RTCVCC at PWR side S Q17A DMN65D8LDW-7 2N SOT363-6 Q17B DMN65D8LDW-7 2N SOT363-6 2 D BI_GATE# Q16 2N7002K_SOT23-3 S R246 10K_0402_5% C271 0.1U_0402_16V4Z 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D DC INTERFACE Rev 1.0 Bay Trail M LA-B511P Thursday, March 13, 2014 Sheet E 25 of 39 A B @ PJP101 ACES_50305-00441-001_4P 1 DC_IN_S1 D VIN EMI@ PL101 HCB2012KF-121T50_0805 EMI@ PC102 100P_0603_50V8 2 GND GND C EMI@ PC103 1000P_0603_50V7K 2 3 @PR111 @ PR111 0_0402_5% +3VLP - PBJ101 @ + PR112 560_0603_5% PR113 560_0603_5% +CHGRTC +RTCBATT ML1220T13RE 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/9/25 Deciphered Date 2014/09/25 Title DCIN / RTC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: A B C Thursday, March 13, 2014 D Sheet 26 of 39 A B C D Ezel battery conn @ PR204 10K_0402_1% BI @ PU201 @ PR206 100K_0402_1% VCC TMSNS1 MAINPWON +RTCVCC OT1 TMSNS2 OT2 RHYST2 @ PR207 47K_0402_1% @ PH201 S THERM_ 100K 1% 0402 B25/50 4250K G718TM1U_SOT23-8 BATT+ GND RHYST1 1 EMI@ PC201 1000P_0402_50V7K BI_GATE BI_GATE D PR212 100K_0402_1% 2 2 @ PR205 10K_0402_1% PR211 0_0402_5% Conn@ EMI@ PL201 HCB2012KF-121T50_0805 @ PC202 0.1U_0603_25V7K BATT_TEMP ACES_50458-00801-001 +3VLP PR201 6.49K_0402_1% PR210 1K_0402_1% 1 EC_SMB_CK1 +3VLP EC_SMDA EC_SMCK TH BI_1 BATT_S1 PR209 100_0402_1% 2 PR208 100_0402_1% EC_SMB_DA1 PJP201 1 2 3 4 5 6 7 8 GND 10 GND S G PQ205 2N7002KW_SOT323-3 For KB9012 OTP ℃ 56℃ 92 For KB9022 OTP 1.2V 1.0V 1.2V 1.0V Need confirm the setting For KB9022 sense 20mΩ Active Recovery PR216 22.6K ohm32.4K ohm 42.8W,0.43V 34.4W,0.43V 40W PR227 26.1K ohm30.9K ohm +EC_VCCA ADP_I 1 PR216 16.9K_0402_1% 2 PR202 10K_0402_1% VCIN0_PH B+ @ PR227 26.1K_0402_1% MAINPWON VCIN1_PROCHOT @ PR223 162K_0402_1% @9022@ PR230 80.6K_0402_1% H_PROCHOT#_EC B value:4250K±1% VCIN1_BATT_DROP PH202 S THERM_ 100K 1% 0402 B25/50 4250K @9022@ PC203 2 @9022@ PR231 0_0402_5% 2 PR203 44.2K_0402_1% PR229 @9022@ 0.1U_0402_25V6 10K_0402_1% 4 ECAGND Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2013/9/25 2014/09/25 Title BATTERY CONN / OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Bay Trail M LA-B511P Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Thursday, March 13, 2014 D Sheet 27 Rev 1.0 of 39 A B C D PQ301 Protection for reverse input G B+ S 2N7002KW _SOT323-3 PR302 SRN SCL PC318 0.1U_0603_16V7K 10 ACIN +3VALW Max 18.12V 17.70V PC322 100P_0402_50V8J L >H H >L Typ 17.63V 17.22V PR319 66.5K_0402_1% Vin Dectector Min 17.16V 16.76V @ PR320 0_0402_5% 2 PR316 316K_0402_1% EC_SMB_CK1 EC_SMB_DA1 ADP_I VILIM = 20*ILIM*Rsr ILIM = 3.3*100/(100+316)/20/0.01 = 3.966 A PC320 0.01U_0402_25V7K PR317 100K_0402_1% BQ24725A_ILIM BQ24725A_IOUT PR318 422K_0402_1% PC321 0.22U_0402_16V7K VIN BQ24725A_ACDET @ PC323 100P_0402_50V8J 1 2 CSON1 CSOP1 PC315 10U_0805_25V6K BQ24725A_BATDRV PC314 10U_0805_25V6K 11 ILIM BATDRV SDA ACOK AON7408L_DFN8-5 12 PR313 10_0603_1% CSOP1 SRP1 PR314 6.8_0603_1% CSON1 SRN1 13 ACDRV PR315 IOUT +3VLP 100K_0402_1% SRP ACDET BQ24725A_ACDRV CMSRC 14 GND BQ24725ARGRR_QFN20_3P5X3P5 ACP 2 BQ24725A_CMSRC DL_CHG PC317 0.1U_0402_25V6 PQ306 BATT+ PL302 PR311 10UH_3.5A_20%_7X7X3_M 0.01_1206_1% CHG PC316 0.1U_0402_25V6 AON7408L_DFN8-5 BQ24725A_LX 15 PC307 0.01U_0402_50V7K 2 PC313 1U_0603_25V6K LODRV Power loss: 0.32W for 3.5A CSR rating: 1W VSRP-VSRN spec < 81.28mV 7X7X3 Isat: 3.8A ACN 2BQ24725A_BATDRV_1 PR305 4.12K_0603_1% PQ305 PR308 0_0603_5% DH_CHG 1 BQ24725A_REGN PD302 RB751V-40_SOD323-2 16 PR307 2.2_0603_5% BQ24725A_BST2 DH_CHG 18 17 BTST PAD VF = 0.37V REGN HIDRV PU301 19 1U_0603_25V6K BQ24725A_BATDRV Rds(on) = 30mohm max Vgs = 20V Vds = 30V ID = 7A (Ta=70C) PC311 0.047U_0402_25V7K 2 PQ304 AO4406AL_SO8 @EMI@ PC319 @EMI@ PR312 680P_0402_50V7K 4.7_1206_5% PR306 10_1206_1% BQ24725A_LX PD301 BAS40CW _SOT323-3 PC312 21 VF = 0.5V PHASE PR310 4.12K_0603_1% PC309 0.1U_0402_25V6 BQ24725A_ACN PR309 4.12K_0603_1% BQ24725A_ACP 2 1 PC308 0.1U_0402_25V6 BQ24725A_ACDRV_1 @EMI@ PC306 0.1U_0402_25V6 VIN PQ303 AO4406AL_SO8 Isat: 4A DCR: 27mohm EMI@ PC305 2200P_0402_25V7K CHG_B+ EMI@ PL301 1UH_NRS4018T1R0NDGJ_3.2A_30% PC304 10U_0805_25V6K PR303 0.02_1206_1% 1 PC302 0.1U_0402_25V6 @ PR304 0_0402_5% PQ302 AON6414AL_DFN8-5 PC301 2200P_0402_50V7K P2 P1 PC303 10U_0805_25V6K VIN Rds(on) = 35mohm max Vgs = 20V Vds = 30V ID = 7.7A (Ta=70C) max Power loss 0.22W for 90W;0.12W for 65W system CSR rating: 1W VACP-VACN spec < 80.64mV Rds(on) typ = 35mohm max Vgs = 20V Vds = 30V ID = 7.7A (Ta=70C) 3M_0402_5% Need check the SOA for inrush 1 1M_0402_5% BQ24725A_VCC2 20 VCC Vgs = 20V Vds = 60V Id = 250mA PC310 0.1U_0402_25V6 PR301 D **Design Notes** #For 65 /90W system, 3S1P/3S2P battery Maximum Charging current 3.5A Maximum Battery discharge power 55W #Register Setting 0X12 bit8 set (default 1) to disable IFAULT HI if add ISN choke #Circuit Design ACOK,ILIM pull high voltage need base on 3/5V enable control Use 10X10 choke and 3X3 H/L Side MOSFET Charge current 3.5A Power loss : 1.82W Power density : 0.81 (15X15) If use 4S per cell 4.35V battery, need additional circuit for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors with PR222 for ACDET setting) PC223 0.22U can't be changed (Wrong adapter concern) For the design, need double confirm PQ202,PQ203,PQ204 rating #Protect function ACOVP : ACDET voltage > 3.14V Charger timeout : No communication within 175s(default) ACOC : 3.33 X Input current DAC setting(default) CHGOCP : 3/4.5/6A based on current current setting BATOVP : 103-106% BATLOWV : 2.5V TSHUT : 155C IFAULT HI : 750mV (default) IFAULT LOW : 150mV (default) Close EC chip Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2013/9/25 Deciphered Date 2014/09/25 Title Charger Bay Trail M LA-B511P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Thursday, March 13, 2014 D Sheet 28 Rev 1.0 of 39 A B C D E 1 EN1 and EN2 dont't floating PR402 499K_0402_1% PU401 PC406 10U_0805_25V6K 3V_VIN EN2 IN EN1 FB BS 3V5V_EN BST_3V 3V_FB PR401 1_0603_5% PC402 0.022U_0402_25V7K PL402 PR412 100K_0402_5% 3.3V LDO 150mA~300mA SPOK PC410 22U_0603_6.3V6M PC409 22U_0603_6.3V6M 1 PC408 22U_0603_6.3V6M 1 PC411 4.7U_0603_6.3V6M +3VALWP @ PC407 22U_0603_6.3V6M +3VLP PR405 3V_SN LDO 1.5UH_PCMB053T-1R5MS_6A_20% 680P_0603_50V7K 4.7_1206_5% PG @EMI@ OUT PC412 2 GND LX_3V @EMI@ 10 SY8208BQNC_QFN10_3X3 B+ 0.1U_0603_25V7K LX @ +3VALWP PR403 1K_0402_5% PC403 PC405 10U_0805_25V6K EMI@ PC404 2200P_0402_50V7K EMI@ PL401 HCB2012KF-121T50_0805 @EMI@ PC401 0.1U_0402_25V6 B+ PR404 150K_0402_1% ENLDO_3V5V Vout is 3.234V~3.366V TDC=6A @ PJ401 +3VALWP 2 +3VALW JUMP_43X118 B+ EN1 and EN2 dont't floating EMI@ PL403 HCB2012KF-121T50_0805 5V_VIN @ PJ402 @EMI@ PC418 0.1U_0402_25V6 FB MAINPWON 5V_FB BST_5V @ PR407 0_0603_5% PC416 0.1U_0603_25V7K 2 +5VALW JUMP_43X118 Vout is 4.998V~5.202V TDC=6A PC423 22U_0603_6.3V6M PC422 22U_0603_6.3V6M PC421 22U_0603_6.3V6M 1 PC420 22U_0603_6.3V6M VL +5VALWP 680P_0603_50V7K 4.7_1206_5% LDO PG SY8208CQNC_QFN10_3X3 1.5UH_PCMB053T-1R5MS_6A_20% 5V_SN OUT LX_5V VCC 10 @EMI@ PC425 @EMI@ PR408 LX GND PC424 4.7U_0603_6.3V6M PR409 2.2K_0402_5% 3V5V_EN PC413 PR406 6800P_0402_25V7K 1K_0402_5% 2 PL404 SPOK PC419 4.7U_0603_6.3V6M EC_ON EN BS VCC_3V IN @ EMI@ PC417 2200P_0402_50V7K PC415 10U_0805_25V6K PC414 10U_0805_25V6K +5VALWP PU402 5V LDO 150mA~300mA @PR410 @ PR410 0_0402_5% PC426 4.7U_0402_6.3V6M PR411 1M_0402_1% 3V5V_EN EC VDD0 is +3VL, PC426 UNPOP EC VDD0 is +3VALW, PC426 POP VC 0/1 controlled by SW method so pop 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/9/25 2014/09/25 Deciphered Date Title 3VALW/5VALW Bay Trail M LA-B511P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Sheet Thursday, March 13, 2014 E 29 Rev 1.0 of 39 D D 1.35V_B+ PR501 2.2_0603_5% BOOT_1.35V PC507 10U_0805_6.3V6K VTT C VTTREF_1.35V VTTREF 20 19 VLDOIN BOOT VDDP FB S3 S5 TON EN_0.675VSP PR507 887K_0402_1% FB_1.35V PR506 8.06K_0402_1% +1.35VP B PR509 680K_0402_1% SYSON PC510 0.033U_0402_16V7K PR508 10K_0402_1% +1.35VP 1.35V_B+ DDR_PW ROK MOSFET: 3x3 DFN H/S Rds(on): 27mohm(Typ), 34mohm(Max) Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C VDDQ 10 +5VALW VDD EN_1.35V 11 PR505 100K_0402_5% L/S Rds(on): 9.9mohm(Typ), 13mohm(Max) Idsm: 13.5A@Ta=25C, 11A@Ta=70C GND RT8207MZQW _W QFN20_3X3 TON_1.35V VDD_1.35V +1.35VP AON7506_DFN33-8-5 18 1 PC513 1U_0603_10V6K PQ502 VTTSNS 21 @ PC514 0.1U_0402_16V7K Choke: 7x7x3 Rdc=8.3mohm(Typ), 10mohm(Max) Note: S3 - sleep ; S5 - power off Switching Frequency: 285kHz Ipeak=10A Iocp~13A OVP: 110%~120% VFB=0.75V, Vout=1.515V MOSFET footprint: SIS412DN SUSP# PR510 200K_0402_1% SUSP D S G PQ503 2N7002KW _SOT323-3 PC515 0.1U_0402_16V7K VTTREF_1.35V off on on CS PAD +0.675VSP off off on @EMI@ PC512 680P_0402_50V7K 12 PU501 VTTGND PGND Level L L H +5VALW PR504 5.1_0603_5% 13 LGATE Co-Lay @EMI@ PR503 4.7_1206_5% + B Mode S5 S3 S0 PR502 9.1K_0402_1% CS_1.35V PC508 1U_0603_10V6K UGATE 15 17 16 DL_1.35V PHASE ESR=15m ohm COMMON PART H=4.5 PC509 330U_2.5V_ESR17M_6.3X4.5 SF000002Z00 PC506 10U_0805_6.3V6K SW _1.35V 14 +1.35VP +0.675VSP PC501 0.1U_0603_25V7K PQ501 AON7408L_DFN8-5 PL502 1UH_11A_20%_7X7X3_M +1.35VP DH_1.35V C COMMON PART 0.675Volt +/- 5% TDC 0.84A Peak Current 1.2A 1 PC505 10U_0805_25V6K PC504 10U_0805_25V6K EMI@ PC503 2200P_0402_50V7K @EMI@ PC502 0.1U_0402_25V6 BST_1.35V PGOOD B+ Pin19 need pull separate from +1.35VP If you have +1.35V and +0.675V sequence question, you can change from +1.35VP to +1.35VS EMI@ PL501 HCB2012KF-121T50_0805 @ PJ503 +0.675VSP 2 +0.675VS JUMP_43X39 A Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2013/9/25 Deciphered Date 2014/09/25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title Size Custom Date: 1.35VP/0.675VSP Bay Trail M LA-B511P Document Number Thursday, March 13, 2014 Sheet 30 Rev 1.0 of 39 D D EN pin don't floating If have pull down resistor at HW side, pls delete PR2 PR602 10K_0402_1% SPOK SPOK C 1 C 2 PR603 1M_0402_1% PC602 0.1U_0402_16V7K SY8208DQNC_QFN10_3X3 FB = 0.6V PC612 22U_0603_6.3V6M 2 PR609 Rdown 20K_0402_1% 2 @ PR607 0_0402_5% +3VALW PC611 22U_0603_6.3V6M LDO_3V PC610 22U_0603_6.3V6M Rup PC609 22U_0603_6.3V6M LDO PG BYP PR608 10K_0402_5% ILMT +1.0V_PGOOD PC614 4.7U_0603_6.3V6K +1.0VALWP COMMON PART 10 LX_1.0V LX FB PL602 1.5UH_PCMC063T-1R5MN_9A_20% 2 GND TDC 8A PC601 0.1U_0603_25V7K PC608 330P_0402_50V7K @ PR601 0_0603_5% BST_1.0V1 PR606 13.7K_0402_1% 1 EN BS ILMT_1.0V +3VALW ILMT_1.0V 10U_0805_25V6K PC607 @ IN PC613 4.7U_0603_6.3V6K @ PR605 0_0402_5% B+_1.0V 10U_0805_25V6K PC604 1 LDO_3V PU601 @EMI@ PC606 0.1U_0402_25V6 EMI@ PC605 2200P_0402_50V7K B+ @EMI@ PR604 @EMI@ PC603 4.7_1206_5% 680P_0603_50V7K 2SNB_1.0V EMI@ PL601 HCB2012KF-121T50_0805 Pin BYP is for CS Common NB can delete The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high B VFB=0.6V Vout=0.6V* (1+Rup/Rdown) Vout=1.011V +1.0VALWP +3VALW and PC614 B 1 PJ601 2 JUMP_43X118 +3VS PR610 2.55K_0402_1% SUSP# PU602 PL603 1UH_2.8A_30%_4X4X2_F +1.05VSP COMMON PART SY8003DFC_DFN8_2X2 PR614 15K_0402_1% Rup FB_1.05V Note:Iload(max)=3A PR615 20K_0402_1% @ PJ603 +1.05VSP 1 2 +1.05VS A JUMP_43X79 Rdown FB=0.6V @EMI@ PC620 680P_0402_50V7K A LX_1.05V NC PC619 22U_0603_6.3V6M PGND PC618 22U_0603_6.3V6M LX EN IN PG PC616 22U_0805_6.3VAM FB PC617 68P_0402_50V8J JUMP_43X79 2 Note:Iload(max)=2.5A @ PJ602 +3VALW PGND SGND @EMI@ PR613 4.7_0603_5% @ PR612 1M_0402_5% 2 @ PR611 100K_0402_5% PC615 0.1U_0402_16V7K 1 +1.05VSP_ON +1.0VALW @ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/9/25 Deciphered Date 2014/09/25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: 1.05VS/1.0VALW Bay Trail M LA-B511P Document Number Thursday, March 13, 2014 Sheet 31 Rev 1.0 of 39 2 @ PJ701 JUMP_43X79 1 +3VALW Ultra Low Dropout 0.23V(typical) at 3A Output Current D @ PC702 1U_0402_6.3V6K D +1.5VSP @ PJ702 2 +1.5VS JUMP_43X79 PC704 0.01U_0402_25V7K PC705 22U_0603_6.3V6M 1 Rup @ PR702 100K_0402_5% @ PR704 22K_0402_5% 2 +1.5VSP PR703 20K_0402_1% 1 2 PC701 0.15U_0402_10V6K +3VS GND PR701 51K_0402_1% SUSP# SUSP# PU701 APL5930KAI-TRG_SO8 VCNTL VOUT VIN VIN VOUT EN POK FB PC703 4.7U_0805_6.3V6K PR705 22.6K_0402_1% Rdown C C +3VALW Vout=0.8V* (1+Rup/Rdown)=1.507V Ultra Low Dropout 0.23V(typical) at 3A Output Current @ PC706 1U_0402_6.3V6K +1.8VALWP +1.8VALWP @ 1 B PJ704 2 +1.8VALW JUMP_43X79 PC709 0.01U_0402_25V7K PC710 22U_0603_6.3V6M 2 PR708 20K_0402_1% Rup 2 @ PR707 100K_0402_5% PU702 APL5930KAI-TRG_SO8 VCNTL VOUT VIN VIN VOUT EN POK FB GND +3VS PC708 0.1U_0402_16V7K 2 @ PR709 22K_0402_5% SPOK PR706 20K_0402_1% B PC707 4.7U_0805_6.3V6K 2 @ PJ703 JUMP_43X79 PR710 15.8K_0402_1% Rdown Vout=0.8V* (1+Rup/Rdown)=1.81V A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/9/25 2014/09/25 Deciphered Date Title 1.5VSP/1.8VALWP Bay Trail M LA-B511P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Thursday, March 13, 2014 Sheet 32 Rev 1.0 of 39 C D @ PC802 1000P_0402_50V7K +CPU_B+ PC808 470P_0402_50V7K 2 PR803 PC809 499_0402_1% 1000P_0402_50V7K 2 +SOC_VNN PL802 0.36UH_PDME064T-R36MS_24A_20% PHASEA_GFX PR815 1_0402_5% PR814 3.65K_0603_1% VSUMG- Rds=13.5mΩ(Typ) 16.5mΩ(Max) 1 2 1.91K_0402_1% 2 PQ804 AON6554_DFN5X6-8-5 LGA_GFX PC814 1000P_0402_50V7K 2 PC813 2 BOOTA_GFX PR812 2.2_0603_5% 0.1U_0603_25V7K VSUMG+ PR807 2.05K_0402_1% PR808 2K_0402_1% PR816 0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 16.8~24A PQ803 AON7518_DFN8-5 PR809 21K_0402_1% PC812 0.047U_0402_25V7K PC811 0.1U_0402_16V7K PR811 11K_0402_1% +3VALWP UGA_GFX-1 @EMI@ PC815 @EMI@ PR813 680P_0402_50V7K 4.7_1206_5% PR806 137K_0402_1% PR804 0_0603_5% OCP setting=21A PR805 324_0402_1% UGA_GFX PC807 120P_0402_50V8 PH802 10K_0402_1%_B25/50 3370K PR810 2.61K_0402_1% 2 PC810 0.1U_0402_16V7K Design Note This circuit is for ULV 1+1 17W CPU: IccMax=33A, TDC=16A(TDP NOM) Loadline: -2.9 m V/A Output Cap follow Intel PDDG VSUMG+ 330uF/9m*3, 22uF_0805*12, 2.2uF_0402*16 GFX(GT2): IccMax=33A, TDC=21.5A Loadline: -3.9 m V/A Output Cap follow Intel PDDG 330uF/9m*2, 22uF_0805*6, 10uF_0603*6 , 1uF_0402*11 COMMON PART VSUMG- 1 PR802 2K_0402_1% PC804 6800P_0402_25V7K Close GFX choke PC805 10U_0805_25V6K PC803 0.01UF_0402_25V7K VGFX_VSNS E Layout Note Reduce Acoustic Noise The AL bulk capacitor of B+ should be very close to CPU_CORE MOSFET Input ceramic caps must place on symmetry same location on top side and bottom side PC806 10U_0805_25V6K B A BOOTA_GFX UGA_GFX PHASEA_GFX 2 1 BOOT_CPU + 2@ PR827 1.91K_0402_1% +CPU_B+ COMMON PART Close CPU L/S MOS OCP setting=18A PQ801 AON7518_DFN8-5 PL803 0.36UH_PDME064T-R36MS_24A_20% A COMMON PART PR832 3.65K_0603_1% PR833 1_0402_5% Cn = L/((Rntcnet*Rsum)/(Rntcnet+Rsum))*DCR) If Cn is correctly selected, when the load current has a square change, the output voltage also has a square response Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/9/25 Deciphered Date 2014/09/25 Title CPU_CORE/GFX_CORE Bay Trail M LA-B511P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D Document Number DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: B +SOC_VCC PC833 0.1U_0402_16V7K VSUM+ 2 Rds=13.5mΩ(Typ) 16.5mΩ(Max) @EMI@ PC825 @EMI@ PR831 680P_0402_50V7K 4.7_1206_5% PQ802 AON6554_DFN5X6-8-5 PH804 10K_0402_1%_B25/50 3370K PR836 2.61K_0402_1% LG1_CPU VSUM- @ PC834 330P_0402_50V7K PC835 0.01UF_0402_25V7K PC824 2 PR830 2.2_0603_5% 0.1U_0603_25V7K BOOT_CPU 1 11K_0402_1% PR840 PC830 0.1U_0402_16V7K 1 Layout Note VCORE_VSNS SVID routing Alert# signal must be routed between the Clock and Date lines to reduce the cross talk between them Signal order arrangement: mobile order is Clock-Alert-Date VCORE_GSNS SVID spacing requirement is 18mils(0.475mm) Maximum total microstrip routing length of each SVID signal must not exceed 6000mils(152.4mm) The SVID bus must be ground reference, It cannot be referenced to input (Vbat or 12V) power plans as they can couple noise into the SVID bus as power states change Avoid routing under noisy circuit, e.g switch node , Gate driver, B+, Vin, high speed signal When SVID signal changes Layer, GND return path may be changed also We need add GND via for GND reference PHASE1_CPU Close CPU choke 1 PR842 137K_0402_1% PC829 0.047U_0402_25V7K PC831 1000P_0402_50V7K 2 PR839 280_0402_1% PC828 120P_0402_50V8 2 PR841 1.78K_0402_1% PC832 PR838 6800P_0402_25V7K 2K_0402_1% 2 PC827 470P_0402_50V7K 2 PR837 499_0402_1% VSUM+ PR835 66.5K_0402_1% 0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 16.8~24A UG1_CPU-1 PR828 0_0603_5% VSUM- UG1_CPU VDD source use +5VS and PGOOD source use +3VS Please confirm power on and down sequence, make sure VGATE after CPU_CORE on PR834 2K_0402_1% B+ Height mm 100u_SF000000I80 Height mm 68u_SF000000W00 +1.8VALW PC826 680P_0402_50V7K PC822 33U_25V_M 2 @EMI@ PC823 0.1U_0402_25V6 1 UG1_CPU PHASE1_CPU 17 EMI@ PL801 HCB2012KF-121T50_0805 PC819 10U_0805_25V6K LG1_CPU 18 +CPU_B+ 20 VGATE PR826 27.4K_0402_1% PH801 470K_0402_5%_B25/50 4700K 21 19 EMI@ PC821 2200P_0402_50V7K BOOT1 UGATE1 22 @ PR819 PR821 @PR819 0_0402_5% 1_0402_5% 16 15 ISEN2 PGOOD PHASE1 COMP LGATE1 NTC FB VR_HOT# 23 PR817 and PR826 27.4K ohm for 100 degree 61.9K ohm for 110 degree PC817 1U_0402_6.3V6K VDD PWM2 PC816 1U_0402_6.3V6K 25 UGATEG 27 28 29 30 31 32 33 26 BOOTG PGOODG COMPG FBG RTNG ISUMNG ISUMPG SDA 14 PR829 3.83K_0402_1% PR825 69.8_0402_1% @PC801 @ PC801 0.1U_0402_16V7K 2 0_0402_5% ALERT# ISL95833BHRTZ-T_TQFN32_4X4 24 1 +1.0VS +5VALW 2 @ PR801 499_0402_1% @ PC818 47P_0402_50V8J PR824 69.8_0402_1% NTC @PR823 @ PR823 VCCP 13 VR_HOT# LGATEG SCLK RTN For VR_HOT#, already pull high at power side VR_ON 12 VR_SVID_DATA PR843 20_0402_1% SVID_ALERT# PR844 16.9_0402_1% SVID_DATA PHASEG ISUMN VR_SVID_ALERT# 470K_0402_5%_B25/50 4700K 0_0402_5% NTCG 11 PAD COMMON PART VR_ON VR_SVID_CLK ISUMP @PR820 @ PR820 ISEN1 PR818 3.83K_0402_1% 10 +5VALW LGA_GFX PU801 PR817 27.4K_0402_1% NTCG_1 PH803 PC820 10U_0805_25V6K Close GFX L/S MOS C D Thursday, March 13, 2014 E Sheet 33 of Rev 1.0 39 PWR Rule 需需需需需SPEC Modify 8/6 3 X 330u/9m(47W) X 330u/9m(37W) 24 pcs 22uF and reserve pcs 2013/08/16 D D +SOC_VNN =+VGFX_CORE +SOC_VCC =+CPU_CORE +SOC_VNN +SOC_VCC Output Cap (330uF*2+22uF*4) PC903 PC904 PC905 PC906 2 2 PC913 PC914 PC915 PC916 Output Cap (330uF*3+22uF*4) 2 2 PC917 330U_D2_2V_Y 330U_D2_2V_Y PC918 + 330U_D2_2V_Y 330U_D2_2V_Y + PC902 + @ PC919 330U_D2_2V_Y C Back Side Cap (10uF*1+4.7uF*2+2.2uF*2) PC929 22U_0603_6.3V6M PC907 22U_0603_6.3V6M PC930 22U_0603_6.3V6M PC908 10U_0603_6.3V6M PC909 PC910 10U_0603_6.3V6M 10U_0603_6.3V6M PC911 PC912 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M + +SOC_VCC Package Edge Cap (22uF*3) 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M + PC901 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M +SOC_VNN Package Edge Cap (22uF*3) Back Side Cap (1uF*3) PC920 PC921 PC922 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M PC923 PC924 PC925 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K @ PC926 @ PC927 @ PC928 C 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/9/25 Deciphered Date 2014/09/25 Title CPU/GFX capacitor Bay Trail M LA-B511P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Sheet Thursday, March 13, 2014 34 Rev 1.0 of 39 Version change list (P.I.R List) Item D Fixed Issue Page of for PWR Reason for change Improve ripple voltage Improve part rating HW request Use bead(L22) individ Unify VC0/VC1 setting Raise part rating Prevent burn issue Customer request VC 0/1 controlled by sw method Meet EC request Rev PG# Modify List 30 33 Date Change PL602 from SH00000YE00 to SH000008800 Change PC901,PC902,PC917,PC918 from SGA000026800 to SGA20331E10 Delete PJ501, PJ502 Change PR202, PR203, PR216 Change PR814, PR832 size from 0402 to 0603 Change PQ303, PQ304 from AO4466L to AO4406AL Change PR211 from 100 to Pop PC426 Change +1.8VALW for VGATE pull high 29 26 32 27 26 28 32 Phase 12/30 DVT 12/31 DVT 01/07 01/08 01/10 01/10 01/29 01/29 02/18 DVT DVT DVT DVT PVT PVT PVT D 10 C B 11 12 13 14 15 C B 12 13 14 15 16 A 17 A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/9/25 2014/09/25 Deciphered Date Title PWR_PIR Bay Trail M LA-B511P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Sheet Thursday, March 13, 2014 35 Rev 1.0 of 39 Z5W1M_DVT Power Sequence AC mode 2014-02-21 BIOS:v0.07 EC:v0.07 G3->S0 S0->S3 S3->S0 S0->S5 ACIN ACIN +3VLP +3VLP 220us EC_ON 1.14ms EC_ON D 2.14ms +5VALW +3VALW SPOK SPOK 5.84ms +1.0VALW +1.0VALW 6.66ms +1.8VALW +1.8VALW ON/OFF ON/OFF 11ms EC_RSMRST# 232ms EC_RSMRST# PBTN_OUT# 123ms PBTN_OUT# EC_SLP_S4# 23.6ms EC_SLP_S3# 23.6ms EC_SLP_S4# EC_SLP_S3# 204ms SYSON 217.6ms SYSON C D +3VALW +5VALW 2.4ms +1.35V 3.29ms +1.35V 3.29ms DDR_PWROK C 4.8ms 92.00ms DDR_PWROK 24.9ms VR_ON 2.52ms 22.32ms 36.20ms VR_ON 2.40ms 10.8ms 9.00ms +SOC_VCC 2.52ms +SOC_VNN +SOC_VCC 2.40ms 26.00ms +SOC_VNN 34.00ms 2.52ms 2.52ms VGATE VGATE 27.7ms 27.30ms 48.8ms 40.80ms SUSP# 140us +1.0VS 9.50ms 1.90ms 4.6ms 1.48ms 12.4ms 2.42ms 21.70ms 2.26ms +1.5VS 2.22ms 16.30ms +1.8VS +1.35VS 2.42ms 22.20ms +1.5VS +1.05VS 1.46ms 18.90ms +1.35VS +1.0VS 1.8ms 4.2ms +1.05VS SUSP# 31.12us 10.20ms 16.20ms 3.08ms +1.8VS 3.04ms 56.40ms +3VS 4.00ms 3.92ms B 41.18ms +5VS 30.50ms 8.1ms +0.675VS 1.6ms 39.36ms 32ms 149.6ms KBRST# 152.4ms KBRST# 60.20ms 92ms 172.4ms PMC_CORE_PWROK PMC_CORE_PWROK 60.20ms 93ms 172.4ms DDR_CORE_PWROK 20.4ms DDR_CORE_PWROK B +5VS 8.16ms 5.00ms +0.675VS +3VS 50.7ms 116ms 99.4ms SUSP# 8.8ms PMC_PLTRST# PMC_PLTRST# 44.3ms A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/9/25 Deciphered Date 2014/09/25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: Power Sequence Bay Trail M LA-B511P Document Number Thursday, March 13, 2014 Sheet 36 Rev 1.0 of 39 Version Change List ( P I R List ) Item Page# Title P.08 Date 12/17 Request Owner Page Issue Description HW Solution Description SLP_S3# leak voltage Rev Change Q21 direction 0.2 D D C P.09 12/17 HW GPIO_S0_SC_56 pull down no vedio Touch screen and touch pad SMbus net fail Pop R53, unpop R55 Change Q2.1 to SOC_I2C5_CLK Change Q3.1 to SOC_I2C2_CLK NO support CPU Thermal sensor Unpop U28 0.2 P.14 1/6 HW U9 DP to LVDS chip old symbol Link CIS for SA00007A300 0.2 P.18 1/6 HW U14 Lid switch old symbol Link CIS for SA000079D00 0.2 P.19 1/6 HW Vendor request to meet Acer spec Change R188,R192 from 47ohm to 60.4ohm 0.2 ESD ESD test Fail Add C277,C278,L19,L20 for RING2 & SLEEVE Change D9 pin2.3 name to RING2_L & SLEEVE_L HW ohm R-short R13,R71,R72,R118,R119,R120,R121,R122, R123,R124,R125,R34,R36,R200,R254,R255, R172,R187,R193,R167,R168,R169,R170, R187,R193,R107,R108,R212 C P.6,8,11,15, 16,17,19,22 1/6 P.17 1/6 HW Change LAN power Unpop U19,C188 Pop R160,R200 change R200.2 from LAN_PWR_EN to LAN_GPO Change C204,C205 from 12pF to 10pF 0.2 P.22 1/6 HW Add EC GPIO Board ID Add LAN_GPO for U22.pin106 Change R211 to 12K 0.2 P.15 1/6 ESD Add D13 0.2 0.2 B B 10 P.21 11 P.19 12 13 1/6 HW Change USB HUB to GL850S Delete U18,R152~R157,C182~C187,Y3 Add U29,R259~R263,C279~C287,Y5 1/6 HW BOM Change C215,C273 from SE107105ML0 to SE080105K80 0.2 P.8 1/6 HW P.13 1/7 EMI Change R34.2 from TS_INT#_CPU to SOC_TS_INT# Change R36.2 from TP_INT#_CPU to SOC_TP_INT# P.23 1/7 0.2 Add L21,L22 for EMI 0.2 Change net name to +1.35V_L C91~C102,R77,R75,(JDIMM1 pin75,76,81,82,87,88, 93,94,99,100,105,106,111,112,117,118,123,124) A 14 0.2 HW Add U30,C288,C289,R264 for +3V_TP Change JTP1.8,R233.2,R225.2,R227.2 to +3V_TP Compal Secret Data Security Classification Issued Date 2011/08/31 2012/08/31 Deciphered Date Title A 0.2 Compal Electronics, Inc EE P.I.R (1) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: Thursday, March 13, 2014 Sheet 37 of 39 Version Change List ( P I R List ) Item Page# 15 Title P.24 Date 01/07 Request Owner Page Issue Description HW BOM Solution Description Rev Change U24,U26 to SA00006FD00 0.2 D D 16 P.9,23 01/08 HW BOM 17 P.8,15,17 19,22 01/08 HW BOM 18 P.23 01/08 HW BOM Delete TP@ BOM structure ==> C255,Q11,R223,R225,R227,R230,R63,R64,Q3 R-short==>R34,R36,R200,R254,R255,R172,R187, 0.2 R193,R167,R168,R169,R170,R187,R193,R107,R108, R212,R150,R151,R248,R249 Pop U30,C288,C289 Unpop R264 Pop U30,C288,C289 Unpop R264 P.08 C 0.2 0.2 19 P.23 P.22 01/08 HW Change U30.3 from SYSON to TP_PWR_EN Add U22.98 TP_PWR_EN 0.2 20 P.21 01/08 ME JUSB2 Link CIS symbol ==> ACES_51524-0140N-001 0.2 21 P.21 01/13 HW USB2.0 port0 USB2.0 port1 22 P.9,14 01/14 HW Change RP10,RP11 to 2.2K_0804_8P4R 0.2 23 P.15 01/14 HW BOM ETS@ BOM structure ==> 0.2 24 P.21 01/16 HW BOM BOM structure==>Add U16,R257 to TPM@ 0.2 25 P.09 02/18 HW BOM For +1.8VS abnormal voltage Pop R28 0.3 26 P.20 02/18 HW 0.3 27 P.24 02/18 HW For HP Change Change For TP Change Change 28 P.23 02/18 HW 29 P.25 02/18 HW 30 P.24 02/18 HW conn  USB3.0 USB HUB C 0.2 R101,R102,R113,R114 B A B pop noise R188,R192 to 0ohm R187,R193 to 60.4ohm 0.3 R205,R206 to +3V_TP JTP1 pin define For Board ID Pop R219 Change R221 to 15K For +1.0 VS Pop C268, Change R242 to 1K unpop SW2 Compal Secret Data Security Classification Issued Date 2011/08/31 2012/08/31 Deciphered Date Title 0.3 A 0.3 0.3 Compal Electronics, Inc EE P.I.R (2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: Thursday, March 13, 2014 Sheet 38 of 39 Version Change List ( P I R List ) Item Page# 31 Title P.20,24 Date 02/21 Request Owner Page Issue Description ME Solution Description Rev 蓋蓋蓋 0.3 JKB2,JBL1,JDMIC1 Change footprint to XXXX-S D D 32 P.9,21,22,23 02/21 HW R-short R40,R96,R143,R142,R259,R198,R199,R220 0.3 32 P.9 02/21 HW Add JCMOS2 0.3 33 P.24 02/21 ME 測Chang 測 R231,R233 to 100 ohm 0.3 Change R232,R234 to 470 ohm 34 P.22 02/24 HW Change USB HUB to GL850G Add U31,R265,R266,R267 Delete U29,R262 0.3 35 P.09 02/25 HW 32.768KHz Change C17,C18 to 18pF 0.3 C C 36 P.17,20,25 02/26 HW Change Q9,Q17,Q18 from SB00000DH00 to SB00000ZU00 0.3 37 P.16 03/12 HW R-short R88 1.0 38 P.23 03/13 HW For Board ID Change R221 from 15K to 20K 1.0 39 P.24 03/13 HW Change SW1 from DBG@ to @ 1.0 B B A A Compal Secret Data Security Classification Issued Date 2011/08/31 2012/08/31 Deciphered Date Title Compal Electronics, Inc EE P.I.R (2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Bay Trail M LA-B511P Date: Thursday, March 13, 2014 Sheet 39 of 39 ... LAN_MIDI0+ LAN_MIDI0+LAN_VDD LAN_MIDI1+ LAN_MIDI1LAN_MIDI2+ LAN_MIDI2+LAN_VDD LAN_MIDI3+ LAN_MIDI3+3V_LAN LAN_CLKREQ# PCIE_PTX_C_DRX_P0 PCIE_PTX_C_DRX_N0 CLK_PCIE_LAN CLK_PCIE_LAN# R200 @ 0_0402_5% LAN_GPO... Trail M LA- B511P Date: Thursday, March 13, 2014 Sheet of 39 +3VS 1 AD10 AD12 C9 10P_0402_25V8J 4.02K_0402_1% ICLK_ICOMP 47.5_0402_1% ICLK_RCOMP LAN CLK_PCIE_LAN# CLK_PCIE_LAN WLAN ... RJ45_MIDI0- PR1+ LAN_MIDI1+ LAN_MIDI1- TCT1 TD1+ TD1- LAN_MIDI0+ LAN_MIDI0- LAN_TERMAL T21 RJ45_MIDI0+ Issued Date Compal Electronics,