A B C D E 1 NWQAA Marseille 10G 2 LA-6062P REV 2.0 Schematic Intel Processor(CFD/ARD) / PCH(HM57/HM55/PM55) 2010-03-24 Rev 2.0 3 4 Compal Electronics, Inc Compal Secret Data Security Classification 200910/9 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Cover Page Size B Date: Document Number Rev 2.0 NWQAA LA-6062P M/B W ednesday, March 24, 2010 Sheet E of 59 A B C D E Fan Control Intel Arrandale / Clarksfield PCIE-Express 16X 2.5GHz VGA Thermal Sensor APL5607 Clock Generator ADM1032ARMZ-2 page RTM890N page 14 page 25 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 rPGA-989 Dual Channel page 5,6,7,8,9,10 page 11,12 BANK 0, 1, 2, 1.5V DDRIII 800/1066/1333 MT/s VGA (DDR3) NVIDIA N11M GE1, 64bit with 512MB/1GB USB/B Right CRT FDI X8 page 26 DMI X4 2.7GHz NVIDIA N11P GE1, 128bit with 1GB/2GB Left USB USB port 0,1 page 37 2.5GHz BT conn page 13,14,15,16,17,18,19,20,21,22,23,24 Felica USB port page 38 USB FingerPrinter USB port page 37 USB port page 38 Int Camera USB port page 38 USB port 11 page 25 5V 480MHz LVDS Conn page 25 USB 5V 480MHz EC SMBus HDMI-CEC Level Shifter HDMI Conn page 27 PCIe 1x page 27 page 40 PCIeMini Card WLAN PCIe port PCIeMini Card JET PCIe port page 39 Intel Ibex Peak RTL8105E 10/100M RTL8111E 1G PCIe port RJ45 PCIeMini Card page 39 1.5V 2.5GHz(250MB/s) page 27 PCIeMini Card WiMax USB port 13 SATA port PCIe 1x 5V 3GHz(300MB/s) B-CAS page 38 SATA port page 37 Express Card USB USB port page 39 Express Card PCIe PCIe port page 39 SIM page 39 BGA-951 SATA port Cardreader JMB385C/389C USB port 12 USB port 10 page 39 page 39 SATA HDD 1.5V 2.5GHz(250MB/s) page 40 3G/TV#1 TV#2 5V 3GHz(300MB/s) SATA ODD SATA port page 37 PCIe 1x 1.5V 2.5GHz(250MB/s) page 28,29,30,31,32,33,34,35,36 PCIe port5 page 41 SATA port 5V 3GHz(300MB/s) eSATA SATA port page 37 USB port 5V 480MHz LPC BUS USB USB port page 37 3.3V/1.5V 24MHz HD Audio 3.3V 33 MHz TP& Light Pipe/B LS-6061P page 45 RTC CKT page 28 DC/DC Interface CKT Cap Sensor & Light Sensor/B LS-6062P page 45 LED/B LS-6063P Debug Port ENE KB926 D3/E0 page 44 Touch Pad page 45 Int.KBD page 44 page 36 EC ROM (256KB) page 44 Power Circuit DC/DC page 47,48,49,50,51,52 53,54,55,56 Power On/Off CKT page 45 CIR page 43 page 42 G-Sensor page 44 Int MIC Conn 37 JPIO (HP &page MIC) 37 page 42 Finger Printer/B LS-6065P page 38 200910/9 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/01/23 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC page 45 Date: A SPK Conn page 25 EC SMBus Audio & USB/B LS-6064P page Power/B_FPC DA300006F00 ALC269 page 38 page 43 page 46 HDA Codec MDC 1.5 Conn SPI ROM (4MB) page 28 B C D Block Diagram Document Number Rev 2.0 NWQAA LA-6062P M/B Tuesday, March 23, 2010 Sheet E of 59 DESIGN CURRENT 0.1A +3VL +5VL DESIGN CURRENT 0.1A B+ Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW DESIGN CURRENT 2A +1.8VS SUSP# MP2121DQ SUSP DESIGN CURRENT 4A N-CHANNEL D +5VS D BCPWON SI4800 DESIGN CURRENT 0.5A +5VS_L_BCAS P-CHANNEL AO-3413 KB_LED RT8205EGQW DESIGN CURRENT 400mA +5VS_LED DESIGN CURRENT 300mA +3VS_HDP DESIGN CURRENT 1.6A +5VS_ODD P-CHANNEL AO-3413 +5VS LDO G9191 ODD_EN# P-CHANNEL AO-3413 Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW WOL_EN# P-CHANNEL AO-3413 SUSP DESIGN CURRENT 330mA +3V_LAN DESIGN CURRENT 4A N-CHANNEL +3VS LCD_ENVDD SI4800 P-CHANNEL AO-3415 C DESIGN CURRENT 1.5A +LCD_VDD C BT_PWR# DESIGN CURRENT 180mA P-CHANNEL AO-3413 +BT_VCC FELICA_PWR DESIGN CURRENT 0.5A +FLICA_VCC DESIGN CURRENT 0.5A +3VS_DGPU DESIGN CURRENT 48A +CPU_CORE DESIGN CURRENT 28A +VGA_CORE P-CHANNEL AO-3413 DGPU_PWR_EN P-CHANNEL AO-3413 VR_ON ISL62883HRZ SUSP# or DGPU_PWR_EN APW7138NITRL VTTP_EN Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 18A +VTT APW7138NITRL SUSP# B Ipeak=7A, Imax=4.9A, Iocp min=7.7 DESIGN CURRENT 7A +1.05VS DESIGN CURRENT 3A +1.05VS_DGPU RT8209BGQW B DGPU_PWR_EN P-CHANNEL AO-3413 SUSP# Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 15A +1.5V SUSP RT8209BGQW DESIGN CURRENT 2A N-CHANNEL +1.5V_CPU FDS6676AS SUSP DESIGN CURRENT 2A N-CHANNEL +1.5VS FDS6676AS VGA_PWROK DESIGN CURRENT 10A N-CHANNEL +VRAM_1.5VS FDS6676AS SUSP or 0.75VR_EN# DESIGN CURRENT 1.5A G2992F1U A +0.75VS A GFXVR_EN DESIGN CURRENT 22A ADP3211AMNR2G +GFX_CORE Compal Electronics, Inc Compal Secret Data Security Classification 200910/9 Issued Date Deciphered Date 2010/01/23 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Power Tree Document Number Rev 2.0 NWQAA LA-6062P M/B Tuesday, March 23, 2010 Sheet of 59 A B C D Platform Voltage Rails ( O MEANS ON +RTCVCC +5VL +5VALW +3VL +3VALW +1.5V +5VS Calpella +3VS +1.8VS +VSB power plane SKU CPU PCH UMA(OPT@) Arrandale HM55@/HM57@ Discrete Clarksfield/ HM55@/HM57@/PM55@ Arrandale (DIS@) Optimus Arrandale HM55@/HM57@ (OPT@) X MEANS OFF ) B+ E VGA N/A N11P@/N11M@ N11P@/N11M@ +1.5VS +1.05VS BTO Option Table +0.75VS +CPU_CORE +VGA_CORE HDMI Function +GFX_CORE +VTT State +VRAM_1.5VS explain UMA Discrete/ Optimus BTO IHDMI@ DHDMI@ +3VS_DGPU +1.05VS_DGPU O O O O O O S1 O O O O O O S3 O O O O O X O O O O X X O O O X X X explain O X X X X X BTO BTO S5 S4/AC S5 S4/ Battery only S5 S4/AC & Battery don't exist 3G Device HEX Address +3VS DDR SO-DIMM A0 H 1010 0000 b +3VS DDR SO-DIMM A4 H 1010 0100 b +3VS Clock Generator D2 H 1101 0010 b +3VS New Card +3VS WLAN/WIMAX +3VS Clock Generator +3VS 3G Clarksfield with S3 Power Saving CEC@ M1@ M3@ PSM3@ LAN SLOT1 Fingerprint LAN WIMAX 10/100M TV@ WIMAX@ 8105E@ Felica G-SENSOR description Felica BLUE TOOTH G-SENSOR SKU Felica BLUE TOOTH G-SENSOR Discrete BT@ GSENSOR@ FELICA@ KB Light KB Light 8111E@ FP@ MDC@ CIR@ KBL@ No Power Saving BTO NOPS@ Camera & Mic Discrete Camera & Mic 3D@ Optimus NO3D@ Camera & Mic OPTFH@ CAM@ GPU New Card N11P & N11E Power Saving PS@ New Card N11M VRAM N11P N11E N11M-GE1 N11M-OP1 8PCS@ N11P@ N11E@ N11MGE@ N11MOP@ New Card NEW@ Card reader Function JMB385C/389C explain JMB385C JMB389C BTO JMB385@ JMB389@ SIGNAL Full ON SLP_S3# SLP_S4# SLP_S5# HIGH HIGH HIGH Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH +3VL HDMI-CEC 34 H 0011 0100 b +3VS NVIDIA GPU 9A H 1001 1010 b LOW LOW HIGH G-Sensor 40 H S4 (Suspend to Disk) +3VS 0100 0000 b +3VS Light Sensor 52 H 0101 0010 b S5 (Soft OFF) LOW LOW LOW G3 LOW LOW LOW Cap Sensor CIR CIR OPT@ HEX +3VL Modem Modem S3 Power Saving explain EC SM Bus2 Address DIS@ Smart Battery Address Fingerprint 3D Panel Device HEX KB Light Fingerprint Optimus Power Device CIR LVDS +3VL Power Modem Giga SKU S3 Power Saving STATE Clarksfield BLUE TOOTH Function description EC SM Bus1 Address Arrandale description Power Clarksfield CEC TV Tuner 3G@ Function PCH SM Bus Address COMMON HDMI@ SLOT2 description explain Arrandale MINI PCI-E SLOT Function S0 CPU HDMI description Virtual I2C 200910/9 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/01/23 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Notes List Rev 2.0 NWQAA LA-6062P M/B Date: A B C D Tuesday, March 23, 2010 Sheet E of 59 JCPUB C488 VTTPWROK_CPU +VTT TP_SKTOCC# AH24 SKTOCC# 49.9_0402_1% CATERR# AK14 CATERR# PECI PECI AT15 THERMAL R18 D T41 PAD PECI Power has removed VR_TT# H_PROCHOT# 68_0402_5% R9 +VTT +VTT H_THERMTRIP# H_THERMTRIP# AN26 AK15 PROCHOT# THERMTRIP# BCLK_ITP BCLK_ITP# AR30 AT30 PEG_CLK PEG_CLK# E16 D16 CLK_CPU_XDP_R CLK_CPU_XDP CLK_CPU_XDP#_R R41 @ 0_0402_5% CLK_CPU_XDP# R42 @ 0_0402_5% CLK_PEG CLK_PEG CLK_PEG# CLK_PEG# DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] PM_EXT_TS#[0] PM_EXT_TS#[1] XDP_RST#_R PMSYNCH 0_0402_5% +1.5V_CPU RESET_OBS# AL15 PM_SYNC H_PWRGOOD1_R R25 AN14 VCCPW RGOOD_1 H_PWRGOOD H_PWRGOOD AN27 VCCPW RGOOD_0 C AP26 PMSYNCH PWR MANAGEMENT H_CPURST# 1K_0402_5% R36 R28 1.1K_0402_1% NOPS@ DRAMPWROK VTTPWROK_CPU DRAMPWROK AK13 SM_DRAMPW ROK VTTPWROK_CPU AM15 VTTPW RGOOD TAPPWRGD AM26 TAPPW RGOOD AL14 RSTIN# DRAMPWROK R29 3K_0402_1% NOPS@ BUF_PLT_RST#_R BUF_PLT_RST# 1.5K_0402_1% R30 R31 750_0402_1% R29 750_0402_1% PS@ JTAG & BPM H_CPURST# Unused by Clarksfield rPGA989 AN15 PM_EXTTS#0 AP15 PM_EXTTS#_R R12 AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# AN25 XDP_DBRESET# IC,AUB_CFD_rPGA,R0P9 PM_EXTTS#0 R6 R7 R8 PRDY# PREQ# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] +VTT SM_DRAMRST#_CPU AL1 SM_RCOMP_0 AM1 SM_RCOMP_1 AN1 SM_RCOMP_2 R10 68_0402_5% @ F6 CLK_CPU_BCLK CLK_CPU_BCLK# DDR3 Compensation Signals Layout Note:Please these resistors near Processor 100_0402_1% 24.9_0402_1% 130_0402_1% 0_0402_5% R312 1K_0402_5% XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_PRDY# R40 XDP_PREQ# R51 XDP_TCK R449 XDP_TMS R450 XDP_TRST# R453 XDP_BPM#0 R454 XDP_BPM#1 R452 XDP_BPM#2 R451 XDP_BPM#3 R455 XDP_DBRESET# R456 @ @ @ @ @ @ @ @ @ @ @ XDP_BPM#0_R XDP_BPM#1_R PS@ R123 100K_0402_5% DRAMPWROK 1.5K_0402_1% H_PWRGOOD TAPPWRGD SM_DRAMRST# Q41 BSS138_NL_SOT23-3 PS@ R32 R35 @ @ 1K_0402_5% H_PWRGOOD_R TAPPWRGD_R 0_0402_5% CLK_CPU_XDP CLK_CPU_XDP# +VTT XDP_RST#_R XDP_DBRESET#_R RST_GATE 2 C140 0.047U_0402_25V6K PS@ C1 0.1U_0402_10V6K @ Add C140 for RST_GATE Glitch issue R14 51_0402_5% 1 SN74AHC1G08DCKR_SC70-5 PS@ XDP_TDO_M @ R21 0_0402_5% XDP_TDO @ R26 0_0402_5% R27 0_0402_5% C JTAG MAPPING Scan Chain (Default) STUFF -> R20, R23, R27 NO STUFF -> R21, R26 CPU Only STUFF -> R20, R21 NO STUFF -> R23, R26, R27 GMCH Only STUFF -> R26, R27 NO STUFF -> R20, R21, R23 R11 51_0402_5% 0_0402_5% XDP_TDO XDP_TRST#_R XDP_TDI XDP_TMS_R XDP_TCK_R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 @ GND GND 25 26 @ R33 P G R52 G O IN2 D IN1 XDP_TDI XDP_TDO_R XDP_PRDY#_R 0_0402_5% XDP_PREQ#_R 0_0402_5% XDP_TCK_R 0_0402_5% XDP_TMS_R 0_0402_5% XDP_TRST#_R 0_0402_5% XDP_BPM#0_R 0_0402_5% XDP_BPM#1_R 0_0402_5% XDP_BPM#2_R 0_0402_5% XDP_BPM#3_R 0_0402_5% XDP_DBRESET#_R 0_0402_5% 0_0402_5% S VTTPWROK 0_0402_5% XDP_TDI_M XDP_BPM#2_R XDP_BPM#3_R PS@ R20 B SM_DRAMRST#_CPU U10 XDP_TDI_R XDP Connector R19 1 10K_0402_5% +3VS NOPS@ VTTPWROK XDP_DBRESET# JXDP PS@ C163 0.1U_0402_16V4Z PM_EXTTS#_R R13 D R23 0_0402_5% XDP_PREQ#_R XDP_PRDY#_R +3VALW 10K_0402_5% Routed as a single daisy chain For S3 CPU Power Saving B PM_EXTTS# Close to CPU for EMI AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 R15 COMP0 @ 1000P_0402_50V7K CLK_CPU_BCLK CLK_CPU_BCLK# COMP1 A16 B16 BCLK BCLK# CLOCKS DRAMPWROK COMP2 DDR3 MISC C487 COMP3 MISC @ 1000P_0402_50V7K H_COMP3 AT23 20_0402_1% H_COMP2 AT24 20_0402_1% H_COMP1 G16 49.9_0402_1% H_COMP0 AT26 49.9_0402_1% R1 R2 R4 R3 MOLEX_52435-2472 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 200910/9 2010/01/23 Deciphered Date Title CPU_CLK/MISC/JTAG/XDP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 2.0 NWQAA LA-6062P M/B Date: Wednesday, March 24, 2010 Sheet of 59 FAN Control Circuit +5VS 1A JFAN C3 10U_0805_10V4Z D U1 +FAN1 EN_DFAN1 10mil EN VIN VOUT VSET GND GND GND GND DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 D24 G24 F23 H23 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 D25 F24 E23 G23 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 E22 D21 D19 D18 G21 E19 F21 G18 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_FSYNC0 FDI_FSYNC1 FDI_FSYNC0 FDI_FSYNC1 F17 E17 FDI_INT FDI_INT C17 FDI_LSYNC0 FDI_LSYNC1 FDI_LSYNC0 FDI_LSYNC1 F18 D17 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT FDI_LSYNC[0] FDI_LSYNC[1] Intel(R) FDI B DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS DMI C DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] Close to CPU FDI_INT FDI_FSYNC0 FDI_FSYNC1 A FDI_LSYNC0 FDI_LSYNC1 DIS@ R689 DIS@ R690 DIS@ R695 DIS@ R696 DIS@ R697 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% C4 1000P_0402_25V8J @ GND GND B26 A26 B27 A25 PEG_COMP R38 R34 PEG_RBIAS R39 750_0402_1% PCIE_GTX_C_CRX_N0 PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_N4 PCIE_GTX_C_CRX_N5 PCIE_GTX_C_CRX_N6 PCIE_GTX_C_CRX_N7 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_N15 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PCIE_GTX_C_CRX_P0 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_P15 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N15 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N15 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P15 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P15 PCIE_GTX_C_CRX_N[0 15] 10K_0402_5% +3VS FAN_SPEED1 49.9_0402_1% K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 D ACES_85204-0300N C6 0.01U_0402_16V7K @ PCI EXPRESS GRAPHICS A24 C23 B22 A21 APL5607KI-TRG_SO8 C5 10U_0805_10V4Z JCPUA DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 @ +FAN1 C PCIE_GTX_C_CRX_P[0 15] PCIE_CTX_C_GRX_N[0 15] B PCIE_CTX_C_GRX_P[0 15] A @ IC,AUB_CFD_rPGA,R0P9 200910/9 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/01/23 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC CPU_DMI/FDI/PEG/FAN Rev 2.0 NWQAA LA-6062P M/B Date: Wednesday, March 24, 2010 Sheet of 59 JCPUC JCPUD DDR_B_D[0 63] C B DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_CAS# DDR_A_RAS# DDR_A_W E# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 SA_BS[0] SA_BS[1] SA_BS[2] DDR_A_CAS# DDR_A_RAS# DDR_A_W E# AE1 AB3 AE9 SA_CAS# SA_RAS# SA_WE# SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] AA6 AA7 P7 DDRA_CLK0 DDRA_CLK0# DDRA_CKE0 SA_CK[1] SA_CK#[1] SA_CKE[1] Y6 Y5 P6 DDRA_CLK1 DDRA_CLK1# DDRA_CKE1 SA_CS#[0] SA_CS#[1] AE2 AE8 DDRA_SCS0# DDRA_SCS1# SA_ODT[0] SA_ODT[1] AD8 AF9 DDRA_ODT0 DDRA_ODT1 DDRA_CLK0 DDRA_CLK0# DDRA_CKE0 DDRA_CLK1 DDRA_CLK1# DDRA_CKE1 DDRA_SCS0# DDRA_SCS1# DDRA_ODT0 DDRA_ODT1 Unused by Clarksfield rPGA989 DDR_A_DM[0 7] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 SA_CK[0] SA_CK#[0] SA_CKE[0] B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_DQS#[0 7] DDR_A_DQS[0 7] DDR_A_MA[0 15] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_CAS# DDR_B_RAS# DDR_B_W E# DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] DDR_B_CAS# DDR_B_RAS# DDR_B_W E# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 DDRB_CLK0 DDRB_CLK0# DDRB_CKE0 SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 DDRB_CLK1 DDRB_CLK1# DDRB_CKE1 SB_CS#[0] SB_CS#[1] AB8 AD6 DDRB_SCS0# DDRB_SCS1# SB_ODT[0] SB_ODT[1] AC7 AD1 DDRB_ODT0 DDRB_ODT1 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDRB_CLK0 DDRB_CLK0# DDRB_CKE0 D DDRB_CLK1 DDRB_CLK1# DDRB_CKE1 DDRB_SCS0# DDRB_SCS1# DDRB_ODT0 DDRB_ODT1 Unused by Clarksfield rPGA989 DDR_B_DM[0 7] C DDR SYSTEM MEMORY - B DDR_A_D[0 63] DDR_B_DQS#[0 7] DDR_B_DQS[0 7] B DDR_B_MA[0 15] IC,AUB_CFD_rPGA,R0P9 @ A A IC,AUB_CFD_rPGA,R0P9 @ Compal Electronics, Inc Compal Secret Data Security Classification 200910/9 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CPU_DDR3 Size B Date: Document Number Rev 2.0 NWQAA LA-6062P M/B W ednesday, March 24, 2010 Sheet of 59 A (Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom) +VTT +CPU_CORE VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 10U_0805_10V4K Change C144 to 4.5mm height at DVT C144 C267 330U_2.5V_M_R17 C81 10U_0805_10V4K 390U_2.5V_M_R10 C83 10U_0805_10V4K C85 10U_0805_10V4K C89 10U_0805_10V4K C88 10U_0805_10V4K C90 10U_0805_10V4K C92 10U_0805_10V4K C94 10U_0805_10V4K C71 10U_0805_10V4K C87 C91 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K D + AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 + VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 C72 C73 10U_0805_10V4K C74 C75 10U_0805_10V4K C76 C77 10U_0805_10V4K C78 C79 10U_0805_10V4K 22U_0805_6.3V6M 22U_0805_6.3V6M (Place these capacitors under CPU socket, top layer) +CPU_CORE @ 10U_0805_10V4K 10U_0805_10V4K C98 10U_0805_10V4K C99 C100 10U_0805_10V4K 10U_0805_10V4K C101 C102 10U_0805_10V4K C103 C104 10U_0805_10V4K (Place these capacitors on CPU cavity, Bottom Layer) 5/25: Add for power team request C +CPU_CORE +CPU_CORE 22U_0805_6.3V6M 22U_0805_6.3V6M C158 C150 C128 22U_0805_6.3V6M C127 22U_0805_6.3V6M C120 C118 C119 C117 C129 C105 C106 2 2 2 2 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C107 C108 C109 22U_0805_6.3V6M C110 2 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M +CPU_CORE 22U_0805_6.3V6M C111 C112 POWER VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 1.1V RAIL POWER Auburndale:18A CPU CORE SUPPLY B Clarksfield: 21A Auburndale:48A PSI# CPU VIDS C AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Clarksfield: 65A VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR VTT_SELECT AN33 H_PSI# AK35 CPU_VID0 AK33 CPU_VID1 AK34 CPU_VID2 CPU_VID3 AL35 CPU_VID4 AL33 AM33 CPU_VID5 AM35 CPU_VID6 AM34 H_DPRSLPVR_R R62 G15 CRB default setting: VID[6:0]=[0100111] H_PSI# 0_0402_5% H_VTTSELECT CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 H_DPRSLPVR ISENSE VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT AN35 IMVP_IMON AJ34 AJ35 VCCSENSE_R R65 VSSSENSE_R R66 B15 A15 VTT_SENSE VSS_SENSE_VTT C113 22U_0805_6.3V6M C114 C115 22U_0805_6.3V6M 22U_0805_6.3V6M C116 2 22U_0805_6.3V6M B TOP side (under inductor) Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V H_VTTSELECT 22U_0805_6.3V6M VTT Rail +CPU_CORE 1 + + 330U_D2_2.5VM_R9M C123 + 330U_D2_2.5VM_R9M 2 330U_D2_2.5VM_R9M C121 H_VTTSELECT = low, 1.1V H_VTTSELECT = high, 1.05V SENSE LINES D Material Note (+VTT): 390uF/ 10mohm, number are 3, power x1, HW x2 JCPUF +CPU_CORE C122 + C124 C125 @ + 330U_D2_2.5VM_R9M 2 330U_D2_2.5VM_R9M IMVP_IMON 1 0_0402_5% 0_0402_5% R64 VCCSENSE VSSSENSE VTT_SENSE VSS_SENSE_VTT R67 100_0402_1% +CPU_CORE VCCSENSE VSSSENSE Check list: 100_0402_1% +CPU_CORE: 6x 470uF, 12x 22uF, 17x 10uF Close to CPU +VTT: 4x 330uF, 7x 22uF, 8x 10uF A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification IC,AUB_CFD_rPGA,R0P9 @ 200910/9 2010/01/23 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC CPU_POWER-1 Rev 2.0 NWQAA LA-6062P M/B Date: Wednesday, March 24, 2010 Sheet of 59 +1.5V_CPU For EMI +1.5V Q33 +GFX_CORE S S S G D D D D FDS6676AS_SO8 R418 220K_0402_5% PS@ SUSP +VSB D R417 820K_0402_5% PS@ Q46A PS@ SUSP 2N7002DW-T/R7_SOT363-6 C472 0.1U_0402_25V6 PS@ 47P_0402_50V8J Q46B PS@ D 47P_0402_50V8J C179 10U_0805_10V4K PS@ C272 @ C281 @ R424 470_0805_5% PS@ 47P_0402_50V8J C280 @ C279 @ 47P_0402_50V8J PS@ SUSP 2N7002DW-T/R7_SOT363-6 Close to CPU +GFX_CORE 22U_0805_6.3V6M C C247 OPT@ C286 OPT@ 1U_0402_6.3V4Z C250 OPT@ C248 OPT@ 10U_0805_6.3V6M C247 0_0402_5% DIS@ Co-layout with C271 +GFX_CORE C494 + 330U_D2_2VM_R6M @ 22A GRAPHICS Change C271 to OS-CON at PVT C266 OPT@ Clarksfield: 5A Auburndale:3A +VTT 2 C142 VTT1_45 VTT1_46 VTT1_47 FDI C141 22U_0805_6.3V6M J24 J23 H25 OPT@ R510 100_0402_1% GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 AR25 AT25 AM24 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 C147 22U_0805_6.3V6M K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 (Place these capacitors under CPU socket, top layer) VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 0.1U_0402_16V4Z C185 0.1U_0402_16V4Z 1K_0402_5% 1U_0402_6.3V4Z C133 C134 C135 1U_0402_6.3V4Z C136 22U_0805_6.3V6M C137 1U_0402_6.3V4Z 1 C138 +1.5V JUMP_43X79 + C216 For EMI C139 1U_0402_6.3V4Z C JUMP_43X79 PJ31 @ 2 1 1 @ 2 +1.5V_CPU 1U_0402_6.3V4Z 0.1U_0402_16V4Z PJ30 2 390U_2.5V_M_R10 +1.5V_CPU +1.5V 22U_0805_6.3V6M @ @ @ @ (Place these capacitors under CPU socket Edge, top layer) P10 N10 L10 K10 C143 B 10U_0805_10V4K J22 J20 J18 H21 H20 H19 C145 22U_0805_6.3V6M (Place these capacitors under CPU socket, top layer) +1.8VS VCCPLL1 VCCPLL2 VCCPLL3 Clarksfield: 1.35A L26 L27 M26 +1.8VS_H_PLL 1U_0402_6.3V4Z C151 1U_0402_6.3V4Z Auburndale:1.35A IC,AUB_CFD_rPGA,R0P9 0.1U_0402_16V4Z C186 C180 GFXVR_EN T54 PAD GFXVR_IMON GFXVR_DPRSLPVR GFXVR_IMON C205 +VTT 1.1V For EMI 470 ohm +VTT VTT0_59 VTT0_60 VTT0_61 VTT0_62 1.8V Change R136 to for GFX issue OPT@ R136 470_0402_5% Auburndale:18A PEG & DMI 22U_0805_6.3V6M GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 DIS@ Clarksfield: 21A GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 R687 B C146 AM22 AP22 AN22 AP23 AM23 AP24 AN24 GFXVR_EN GFX_VR_EN GFX_DPRSLPVR GFX_IMON 22U_0805_6.3V6M +VTT For S3 CPU Power Saving C257 0.1U_0402_16V4Z 1 OPT@ +GFX_CORE R509 100_0402_1% 0_0402_5% VCC_AXG_SENSE 0_0402_5% VSS_AXG_SENSE R117 OPT@ R142 OPT@ C258 0.1U_0402_16V4Z C249 OPT@ VCC_AXG_SENSE_R VSS_AXG_SENSE_R AR22 AT22 C256 0.1U_0402_16V4Z + VAXG_SENSE VSSAXG_SENSE C160 0.1U_0402_16V4Z C271 330U_2.5V_M_R17 OPT@ VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 - 1.5V RAILS AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 DDR3 10U_0805_6.3V6M GRAPHICS VIDs 1U_0402_6.3V4Z POWER 22U_0805_6.3V6M SENSE LINES JCPUG 1 2 4.7U_0603_6.3V6K C152 R71 0_0805_5% C153 C154 C155 22U_0805_6.3V6M 2.2U_0603_6.3V4Z @ A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 200910/9 Deciphered Date 2010/01/23 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC CPU_POWER-2 Rev 2.0 NWQAA LA-6062P M/B Date: Wednesday, March 24, 2010 Sheet of 59 JCPUI C B JCPUH VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS NCTF D K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 IC,AUB_CFD_rPGA,R0P9 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 H_NCTF1 H_NCTF2 H_NCTF6 H_NCTF7 PAD T4 PAD T5 PAD T6 PAD T7 AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPUE VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 IC,AUB_CFD_rPGA,R0P9 @ AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 +VREF_DQA_M3 +VREF_DQB_M3 WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1 3.01K_0402_1% @ R74 3.01K_0402_1% @ R75 3.01K_0402_1% @ R76 2 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 RSVD32 RSVD33 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 AJ26 AJ27 RSVD_NCTF_40 RSVD_NCTF_41 AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 E15 F15 A2 D15 C15 AJ15 AH15 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 Reserve via for test B19 A19 RSVD15 RSVD16 A20 B20 RSVD17 RSVD18 U9 T9 RSVD19 RSVD20 AC9 AB9 RSVD21 RSVD22 CFG0 - PCI-Express Configuration Select *1:Single PEG 0:Bifurcation enabled C1 A3 CFG3 - PCI-Express Static Lane Reversal *1 :Normal Operation :Lane Numbers Reversed 15 -> 0, 14 -> 1, RSVD_NCTF_23 RSVD_NCTF_24 J29 J28 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 RSVD_NCTF_30 RSVD_NCTF_31 D C B VSS CFG4 - Display Port Presence *1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port @ RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 (SA_DIMM_VREF) RSVD10(SB_DIMM_VREF) RSVD11 RSVD12 RSVD13 RSVD14 RESERVED AP34 IC,AUB_CFD_rPGA,R0P9 @ *:Default A A Compal Electronics, Inc Compal Secret Data Security Classification 200910/9 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CPU_GND/RESERVED Size Document Number Custom Rev 2.0 NWQAA LA-6062P M/B Date: Tuesday, March 23, 2010 Sheet 10 of 59 +3VL Caps Sensor/Light Sensor Conn Touchpad & Light Pipe Connector Power Button JCS SW3 C458 0.1U_0402_25V6 @ EC_ON @ ESB_DAT ESB_CK CAP_INT# CAP_RST# Q7A 2N7002DW-T/R7_SOT363-6 EC_SMB_CK2 EC_SMB_DA2 R396 10K_0402_5% D Remove J3 at PVT For EMI request SW1 10 GND GND SW_L JTPL +5VS TP_CLK TP_DATA TP_LED# KSI6 KSO0 390_0402_5% ACES_85201-0405N @ +5VALW ESB_DAZ @ 100_0402_5% 100P_0402_50V8J ESB_CKZ @ 1 D83 ON/OFFBTN# R428 R427 KSI6 KSO0 C260 @ ON/OFFBTN# R22 10 11 12 SW_L SW_R For EMI PWR_ON_LED# @ D 10 GND GND Q7B SW4 SW_R SMT1-05_4P P-TWO_161021-10021 TP_LED C261 @ 2N7002DW-T/R7_SOT363-6 JPOWER 1 2 3 4 G1 G2 SMT1-05_4P Remove D19 at DVT SMT1-05-A_4P P-TWO_161021-10021 BTM side 10 11 12 ON/OFFBTN# ESB_DAZ ESB_CKZ CAP_INT# CAP_RST# Remove SW2 at pre-MP TOP side +5VALW +3VL FBMA-11-100505-301T_0402 +3VS L13 L14 FBMA-11-100505-301T_0402 51_ON# ON/OFFBTN# 100K_0402_5% @ R395 For debug PWR_ON_LED# 100_0402_5% 100P_0402_50V8J PJSOT05C_SOT23-3 Screw Hole +5VS C R819 10K_0402_5% WIMAX@ WIMAX_LED_GND# 1 H_3P0 @ H_2P7N @ C VGA H3 H4 H_2P9x3P9 @ 1 H_2P9x3P9 @ H16 H_4P7 @ H17 H_3P3 @ H_3P3 @ H_3P3 @ H23 H_4P2x4P7 @ LOGO_LED# H22 H_4P2x4P7 @ H21 H_4P2 @ +5VS H20 HT-SV116BP_WHITE 2 R774 120_0402_5% Q9A 2N7002DW-T/R7_SOT363-6 H15 CPU LOGO_LED 2N7002DW-T/R7_SOT363-6 Q6B 2 R776 120_0402_5% HT-SV116BP_WHITE MDC D20 MINI CARD WLAN H24 H25 H18 H19 H_3P3 @ H_3P3 @ H_3P3 @ H_3P3 @ 2N7002DW-T/R7_SOT363-6 @ R50 0_0402_5% Q9B H14 H_3P0 @ Logo LED D22 H13 H_3P0 @ H26 H_2P7x3P2N @ PCB Fedical Mark PAD FD1 JLED +5VALW +5VS WL_BT_LED# PWR_ON_LED# PWR_SUSP_LED# CR_LEDCON# BATT_FULL_LED# BATT_CHG_LOW_LED# WIMAX_LED_GND# WL_BT_LED# DC_IN PWR_ON_LED# PWR_SUSP_LED# HDD_LED# CR_LEDCON# BATT_FULL_LED# BATT_CHG_LOW_LED# 10 11 12 10 11 12 LED/B Connector FD2 FD3 @ @ FD4 ISPD @ UV1 N11PR3@ U11 N11P-GE1-A3 GND GND B @ @ B HDD_LED# H12 H_3P0 @ MINI CARD 3G SATA_LED# 1 1 H1 H_2P9 @ R404 10K_0402_5% H11 H_3P0 @ Q156A 2N7002DW-T/R7_SOT363-6 WIMAX@ H2 +5VS H10 H_3P0 @ @ Q156B 2N7002DW-T/R7_SOT363-6 WIMAX@ HDD LED H9 H_3P0 @ H8 H_3P0 @ Q35A 2N7002DW-T/R7_SOT363-6 H6 H_3P0 @ LED_WIMAX# DC_IN R506 WIMAX_LED_GND# 0_0402_5% WiMAX LED ACIN H5 DC-IN LED 13 14 UV1 HM55R3@ PCH N11ER1@ UV1 N11MGER1@ UV1 N11MOPR1@ ZZZ PCB LA-6062P U11 PM55@ PJP1 45@ ACES_85201-1205N A N11E-GE1-A3 N11M-GE1-B-A3 N11M-OP1-B-A3 PCH UV1 UV1 UV1 U11 N11ER3@ N11E-GE1-A3 N11M-GE1-B-A3 200910/9 A PCH Title Date: PJP1 HM57@ Compal Electronics, Inc 2010/01/23 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC N11MOPR3@ N11M-OP1-B-A3 Compal Secret Data Security Classification Issued Date N11MGER3@ PWR/Cap./TP/LED/LP/LS/Screw Document Number Rev 2.0 NWQAA LA-6062P M/B Wednesday, March 24, 2010 Sheet 45 of 59 A B C +3VALW TO +3VS +3VALW +3VS D E +5VALW TO +5VS +5VALW Vgs=10V,Id=9A,Rds=18.5mohm +1.5V to +1.5VS Vgs=10V,Id=9A,Rds=18.5mohm +1.5V +5VS +1.5VS 4.7U_0805_10V4Z C469 470_0805_5% Q12A Q12B SUSP 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 R421 470_0805_5% NOPS@ 1 Q44B 2N7002DW-T/R7_SOT363-6 PS@ D Q6A 2N7002DW-T/R7_SOT363-6 SUSP# S Q44A 2N7002DW-T/R7_SOT363-6 PS@ SUSP Q13B 2N7002DW-T/R7_SOT363-6 Q189 SUSP G 2N7002_SOT23-3 0.75VR_EN 100K_0402_5% R158 VTTPWROK R421 47_0805_5% PS@ VGA_PWROK# 2N7002DW-T/R7_SOT363-6 SUSP SUSP PS@ Q13A For S3 CPU Power Saving R429 R431 +VSB 220K_0402_5% R430 820K_0402_5% 2 0.1U_0402_25V6 C481 4.7U_0805_10V4Z C473 C475 4.7U_0805_10V4Z 1U_0402_6.3V4Z FDS6676AS_SO8 +0.75VS 2 +5VALW R422 100K_0402_5% 2 470_0805_5% S S S G R414 820K_0402_5% 0.75VR_EN# D D D D 1 R408 R411 +VSB 220K_0402_5% 2 @ R425 100K_0402_5% PS@ Vgs=10V,Id=14.5A,Rds=6mohm C478 1U_0402_6.3V4Z FDS6676AS_SO8 1 For S3 CPU Power Saving +VRAM_1.5VS Q43 C464 +3VALW +1.5V to +VRAM_1.5VS +1.5V 4 C821 S S S G Q11B SUSP 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 @ D D D D 0.1U_0402_25V6 Q11A C822 C463 C470 R413 200K_0402_5% @ +VSB 4.7U_0805_10V4Z C468 R407 For EMI 0.1U_0402_16V4Z C467 470_0805_5% R410 47K_0402_5% Vgs=10V,Id=14.5A,Rds=6mohm Q31 0.1U_0402_16V4Z Q10B SI4800BDY_SO8 Q10A SUSP 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 1U_0402_6.3V4Z R412 330K_0402_5% +VSB C466 C465 1 0.022U_0402_25V7K 1 R409 47K_0402_5% S S S G R406 D D D D 0.01U_0402_25V7K 4.7U_0805_10V4Z C461 +5VS Q30 1U_0402_6.3V4Z SI4800BDY_SO8 4.7U_0805_10V4Z 4.7U_0805_10V4Z 2 S S S G C460 1 D D D D C459 470_0805_5% Q29 4.7U_0805_10V4Z C462 +5VALW R146 D S Q188 2N7002_SOT23-3 G VGA_PWROK 100K_0402_5% +3VS to +3VS_DGPU +5VS TO +5VS_ODD +3VS +3VALW 2 +5VS_ODD 2 Q206B 2N7002DW-T/R7_SOT363-6 OPT@ C686 1U_0402_6.3V4Z OPT@ Q55 G 2N7002_SOT23-3 OPT@ Issued Date D S 2 1 C680 1U_0402_6.3V4Z Compal Electronics, Inc Compal Secret Data 200910/9 2010/01/23 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: B DGPU_PWR_EN# Security Classification A AO3413_SOT23 C217 0.01U_0402_25V7K PJ28 JUMP_43X79 @ +5VS_ODD 1 Vgs=-4.5V,Id=3A,Rds