135 samsung NP350V

A B C D E 1 QCLA4,5 Eureka 14" & 15" 2 LA-8862P REV 0.2 Schematic Intel Processor(Ivy Bridge / Sandy Bridge) PCH(Panther Point) 2011-11-24 Rev 0.2 3 4 Compal Electronics, Inc Compal Secret Data Security Classification 2011/01/31 Issued Date Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Cover Page Document Number Rev 0.2 QCLA4,5 Thursday, February 16, 2012 Sheet E of 48 A B C D E Intel CPU Ivy Bridge Sandy Bridge eDP Conn Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 rPGA-989 page 13 37.5mm*37.5mm Dual Channel page 5,6,7,8,9,10 CRT page 14 FDI X8 DMI X4 2.7GT/s 5GT/s USB Right 5V 5GT/s USB20 port 2,3 USB30 port 3,4 page 25 USB20 4x LVDS Conn FingerPrinter USB20 3x 5V 480MHz page 15 page 40 USB20 port 0,1 USB30 port 1,2 page 30 Int Camera USB port page 29 USB port 11 page 13 HDMI Conn Intel PCH Panther Point page 15 RJ45 USB Left 5V 480MHz page 13 HDMI-CEC page 11,12 BANK 0, 1, 2, 1.5V DDRIII 1066/1333/1600 MT/s USB30 4x EC SMBus RTL8105E-VD 10/100M RTL8111F-VB 1G 5V 480MHz PCIe Gen1 1x PCIeMini Card WiMax USB port page 27 1.5V 5GT/s PCIe Gen1 1x SATA Gen3 port 1.5V 5GT/s 5V 6GHz(600MB/s) page 31 PCIe port USB20 3x FCBGA-989 PCIeMini Card WLAN PCIe port PCIeMini Card 3G/TV#1 TV#2 USB port 12 USB port 10 page 27 mSATA SATA port page 27 page 27 B-CAS page 26 25mm*25mm Cardreader RTS5229 PCIe port4 PCIe Gen1 1x 1.5V 5GT/s page 29 SATA Gen3 port 5V 6GHz(600MB/s) SATA port SATA ODD SIM page 27 page 16,17,18,19,20,21,22,23,24 5V 3GHz(300MB/s) SATA port page 23 SATA HDD SATA port page 23 PCIe Gen2 2x 1.5V 5GT/s LPC BUS HD Audio 3.3V 33 MHz 3.3V 24MHz USB3.0 Right-side UPD720202 HDA Codec SPI ROM (4MB + 2MB) page 16 Debug Port page 36 ALC280 ENE KB930/KB9012 USB3.0 Left-side UPD720202 PCIe port5 page 31 PCIe port6 page 32 page 33 page 35 RTC CKT page 16 SPK Conn JPIO (HP &page MIC) 34 page 34 DC/DC Interface CKT Touch Pad page 37 page 38 Int.KBD page 36 EC ROM (128KB) page 36 CIR page 35 G-Sensor page 36 4 EC SMBus Power Circuit DC/DC page 39,40,41,42,43, 44,45,46,47,48,49 Finger Printer/B page 26 Power On/Off CKT page 37 Compal Electronics, Inc Compal Secret Data Security Classification 2010/09/03 Issued Date Power/B Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC page 37 Date: A B C D Block Diagram Document Number Rev 0.2 QCLA4,5 Sheet Thursday, February 16, 2012 E of 48 DESIGN CURRENT 0.1A DESIGN CURRENT 0.1A +3VL +5VL B+ Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A DESIGN CURRENT 11A +5VALW DESIGN CURRENT 1.8A +1.8VS DESIGN CURRENT 6.5A +5VS SUSP# SY8033BDBC SUSP D N-CHANNEL D BCPWON SI4800 DESIGN CURRENT 0.1A +5VS_L_BCAS DESIGN CURRENT 0.4A +5VS_LED DESIGN CURRENT 0.3A +3VS_HDP DESIGN CURRENT 1.6A +5VS_ODD P-CHANNEL AO-3413 KB_LED TPS51125 P-CHANNEL AO-3413 +5VS LDO G9191 ODD_EN# P-CHANNEL AO-3413 SYSON Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A SY8036 +1.5V SUSP N-CHANNEL DESIGN CURRENT 5A +1.5V_CPU FDS6676AS SUSP C C N-CHANNEL DESIGN CURRENT 1.5A +1.5VS FDS6676AS 0.75VR_EN# DESIGN CURRENT 1A +0.75VS DESIGN CURRENT 6A +VCCSA DESIGN CURRENT 0.3A +16VS DESIGN CURRENT 7.5A +3VALW DESIGN CURRENT 0.1A +3V_LAN G2992 VCCPPWRGD Ipeak=6A, Imax=4.A, Iocp min=8 SY8037 LNB EN Imax=0.3A, Iocp min=0.8A APW7137 Ipeak=5A, Imax=3.5A, Iocp min=6.2A WOL_EN P-CHANNEL AO-3413 SUSP N-CHANNEL B DESIGN CURRENT 6A +3VS DESIGN CURRENT 2A +LCD_VDD B UMA_ENVDD SI4800 P-CHANNEL AO-3415 FELICA_PWR DESIGN CURRENT 0.1A P-CHANNEL AO-3413 VR_ON NCP6132A +FLICA_VCC DESIGN CURRENT 94A +CPU_CORE DESIGN CURRENT 50A +GFX_CORE DESIGN CURRENT 15A +1.05VS_VCCP SUSP# TPS51212 Ipeak=14A, Imax=9.8A, Iocp min=16.92A A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Tree Size Document Number Rev 0.2 QFKAA Date: Thursday, February 16, 2012 Sheet of 48 A Voltage Rails B ( O MEANS ON +RTCVCC D E X MEANS OFF ) B+ +5VL +5VALW +3VL +3VALW +1.5V +5VS +3VS +1.8VS +VSB power plane C +1.5VS +1.05VS BTO Option Table +0.75VS +CPU_CORE +VGA_CORE +VTT State HDMI Camera & Mic TPM description HDMI Camera & Mic TPM explain HDMI Digital MIC Analog MIC SLB 9635 SLB 9655 WIMAX BTO HDMI@ CAM@ AMIC@ TPM9635@ TPM9655@ WIMAX@ Function +GFX_CORE +VRAM_1.5VS +3VS_DGPU +1.05VS_DGPU O O O O O O S1 O O O O O O S3 O O S5 S4/AC O O O X X O O O O X S5 S4/ Battery only O O O X X X S5 S4/AC & Battery don't exist O X X X X X Half Card SPI ROM Green CLK USB 3.0 Sleep & Charge LAN description SPI ROM Green CLK USB 3.0 Sleep & Charge LAN Function S0 MINI PCI-E SLOT explain WIN8 BTO WIN8@ Green CLK GCLK@ NOGCLK NOGCLK@ Internal 10/100M IUSB30@ Giga 8105ELDO@ 8111FVB@ PCH SM Bus Address Power Device HEX +3VS DDR SO-DIMM A0 H 1010 0000 b +3VS DDR SO-DIMM A4 H 1010 0100 b +3VS Clock Generator D2 H 1101 0010 b +3VS New Card +3VS WLAN/WIMAX +3VS Clock Generator +3VS 3G Address SIGNAL STATE EC SM Bus1 Address EC SM Bus2 Address SLP_S3# SLP_S4# SLP_S5# HIGH HIGH Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH +3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH +3VL HDMI-CEC 34 H 0011 0100 b +3VS NVIDIA GPU 9A H 1001 1010 b +3VS G-Sensor 40 H 0100 0000 b S4 (Suspend to Disk) LOW LOW HIGH +3VS Light Sensor 52 H 0101 0010 b S5 (Soft OFF) LOW LOW LOW G3 LOW LOW LOW Power Device +3VL Cap Sensor HEX Address Full ON HIGH Virtual I2C Compal Electronics, Inc Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Notes List Rev 0.2 QFKAA Sheet Thursday, February 16, 2012 E of 48 JCPUB 100 MHz 1000P_0402_50V7K CC63 PM_DRAM_PWRGD_R CC62 H_PWRGOOD_R H_SNB_IVB# 11,21 H_SNB_IVB# C26 PROC_SELECT# @ D T2 +1.05VS_VCCP 31 RC44 62_0402_5% 10K_0402_5% TP_SKTOCC# PAD H_PECI H_PROCHOT# AN34 H_CATERR# AL33 H_PECI AN33 SKTOCC# CATERR# PECI RC159 31 H_PROCHOT# RC45 PAD THERMAL T1 H_PROCHOT#_R 56_0402_5% AL32 PROCHOT# H_PWRGOOD H_THERMTRIP# 21 H_THERMTRIP# AN32 THERMTRIP# CLOCKS BCLK BCLK# A28 A27 CLK_CPU_DMI CLK_CPU_DMI# Stuff RC157 and RC158 if not support eDP CLK_CPU_DMI 17 CLK_CPU_DMI# 17 +1.05VS_VCCP 120 MHz DPLL_REF_CLK DPLL_REF_CLK# A16 A15 CLK_CPU_EDP CLK_CPU_EDP# CLK_CPU_EDP# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] PRDY# PREQ# @ CC70 1000P_0402_50V7K 1000P_0402_50V7K H_PM_SYNC 18 H_PM_SYNC CC71 H_PM_SYNC CC66 BUF_CPU_RST# @ AM34 PM_SYNC RC187 21 H_PWRGOOD PM_SYS_PWRGD_BUF Please place near JCPU RC58 H_PWRGOOD_R 0_0402_5% PM_DRAM_PWRGD_R 130_0402_5% AP33 V8 UNCOREPWRGOOD SM_DRAMPWROK C BUF_CPU_RST# AR33 RESET# +3VALW_PCH +3VALW_PCH 10K_0402_5% RC13 +3VS R8 H_DRAMRST# AK1 A5 A4 SM_RCOMP_0 RC56 SM_RCOMP_1 RC59 SM_RCOMP_2 RC61 TCK TMS TRST# TDI TDO DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] H_DRAMRST# 2 140_0402_1% 25.5_0402_1% 200_0402_1% DDR3 Compensation Signals Layout Note:Place these resistors near Processor AP29 AP27 @ CC34 180P_0402_50V8J by ESD requestion and place near CPU AR26 AR27 AP30 XDP_TCK_R XDP_TMS_R XDP_TRST#_R AR28 AP26 XDP_TDI_R XDP_TDO_R AL35 D 1K_0402_5% PAD PAD T4 T5 RC55 PAD T6 PAD T7 51_0402_5% Layout request for test point AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 C 0.1U_0402_10V7K CC33 UC1 74AHC1G09GW_TSSOP5 P 0_0402_5% B A O TYCO_2013620-2_IVY BRIDGE RC14 200_0402_5% @ PM_SYS_PWRGD_BUF 18 DRAMPWROK 1K_0402_5% G RC12 @ 18,31 PM_PWROK +1.5V_CPU DRAMPWROK 1 200_0402_5% 2 RC11 JTAG & BPM H_PECI @ PWR MANAGEMENT 2 RC158 H_DRAMRST# 1000P_0402_50V7K RC157 CLK_CPU_EDP SM_DRAMRST# DDR3 MISC 1000P_0402_50V7K MISC @ SUSP SUSP 9,34 RC25 39_0402_5% @ 0_0402_5% @ D RC181 S G QC2 2N7002_SOT23 @ B B FAN Control Circuit Buffered Reset to CPU +5VS JFAN 1A PLT_RST# 20,26,27,28,31,32 +FAN2 A IN OUT GND 10mil BUFO_CPU_RST# RC35 43_0402_1% 1000P_0402_50V7K 5 GND GND ACES_85204-0300N R24 10K_0402_5% +3VS FAN_SPEED1 APL5607KI-TRG_SO8 C17 10U_0805_6.3V6M BUF_CPU_RST# FAN_SPEED1 31 C14 0.01U_0402_25V7K @ 74AHC1G125GW_SOT353-5 RC40 0_0402_5% @ A 2 EN_DFAN1 RC38 75_0402_5% VCC OE# GND GND GND GND @ 1 31 UC2 PLT_RST# EN VIN VOUT VSET U1 @ C15 C13 10U_0805_6.3V6M 0.1U_0402_10V7K CC36 +1.05VS_VCCP +FAN2 +3VS Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/09/03 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Sandy Bridge_JTAG/XDP/FAN Size Document Number Custom Date: Rev 0.2 QFKAA Thursday, February 16, 2012 Sheet of 48 +1.05VS_VCCP D 18 DMI_CTX_PRX_N0 18 DMI_CTX_PRX_N1 18 DMI_CTX_PRX_N2 18 DMI_CTX_PRX_N3 C 18 18 18 18 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 18 18 18 18 18 18 18 18 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 18 18 18 18 18 18 18 18 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 18 FDI_FSYNC0 18 FDI_FSYNC1 18 FDI_INT 18 FDI_LSYNC0 18 FDI_LSYNC1 eDP_COMP signals should be shorted near balls and routed with typical +1.05VS_VCCP impedance H EC_SMB_CK1 31,35 2.4 < Vdetect < 3.15V Min 150K_0402_1% PC243 0.01U_0402_25V7K Vin Dectector & ILIM 2 PR243 270K_0402_1% BQ24725_ILIM PR242 100K_0402_1% VIN BQ24725_ACDET PR240 PR244 154K_0402_1% 18,31 ACIN EC_SMB_DA1 31,35 ADP_I 31,35 Please locate the RC Near EC chip 2011-02-22 Compal Secret Data Security Classification Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Compal Electronics, Inc PWR-CHARGER Document Number Rev 0.2 SAMSUNG Thursday, February 16, 2012 D Sheet 36 of 48 A B C D E 2VREF_8205 PC333 1U_0603_16V6K 1 19 LG_5V PL352 2.2UH_ETQP3W2R2WFN_8.5A_20% NC SNUB_5V VREG5 VIN 18,35 RT8205LZQW(2)_WQFN24_4X4 PQ352 FDMC7692S_MLP8-5 VL PC342 1U_0603_10V6K 2 PR338 100K_0402_1% @ +5VALWP PC359 4.7U_0805_10V6K + @ PC351 220U_6.3V_M LX_5V UG_5V 20 PR356 4.7_1206_5% 21 22 PQ351 AON7408L PR355 PC355 2.2_0402_5% 0.1U_0402_10V7K BST1_5V BST_5V PC356 680P_0402_50V7K 23 14 24 POK 13 PC358 10U_0805_25V6K PC354 2200P_0402_50V7K FB1 REF ENTRIP1 TONSEL 2 ENTRIP2 LGATE1 PR334 499K_0402_1% 1 3/5V_B+ PQ332 FDMC7692S_MLP8-5 FB2 PHASE1 LGATE2 EN PHASE2 @ UGATE1 + 12 LG_3V BOOT1 UGATE2 18 PC336 PR336 680P_0402_50V7K 4.7_1206_5% SNUB_3V PC331 220U_6.3V_M BOOT2 11 LX_3V PGOOD 17 PL332 4.7UH_ETQP3W4R7WFN_5.5A_20% 3/5V_B+ PR357 120K_0402_1% VO1 VREG3 GND +3VALWP VO2 PC335 0.1U_0402_10V7K PR333 2 BST_3V BST1_3V 2.2_0402_5% UG_3V 10 16 ENTRIP2 P PAD PQ331 AON7408L 25 PU330 PC341 10U_0805_6.3V6M PR337 120K_0402_1% PC340 4.7U_0805_25V6-K PC339 2200P_0402_50V7K +3VLP 15 PC338 0.1U_0402_25V6 1 PR351 20K_0402_1% FB_5V FB_3V SKIPSEL PL331 HCB2012KF-121T50_0805 ENTRIP1 PR331 20K_0402_1% 3/5V_B+ B+ PR350 30K_0402_1% PC353 0.1U_0402_25V6 PR330 13K_0402_1% @ ENTRIP2 3 D 2N_3_5V_001 PQ333A SSM6N7002FU_US6 S PR339 100K_0402_5% PJP333 PJP352 +5VALWP +5VALW +3VLP (5A,200mils ,Via NO.= 10) PR341 0_0402_5% +3VALWP +3VL PJP353 +3VALW VL (4A,120mils ,Via NO.= 8) +5VL PAD-OPEN 2x2m PAD-OPEN 4x4m PAD-OPEN 4x4m PJP332 PAD-OPEN 2x2m VL PQ334 DRC5115E0L_SOD323-3 PC343 4.7U_0805_25V6-K 31 VS_ON PQ333B SSM6N7002FU_US6 G PR340 2.2K_0402_1% PC360 0.1U_0603_25V7K D G S 31 EC_ON ENTRIP1 3/5V_B+ 2VREF_8205 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc PWR-3.3VALWP/5VALWP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.2 QCLA4 LA-8861P M/B Thursday, February 16, 2012 Sheet E 37 of 48 0.75Volt +/- 5% TDC 0.7A Peak Current 1A D PL151 HCB1608KF-121T30_0603 B+ 1.5V_B+ D BST_1.5V PR155 +1.5V BOOT_1.5V +0.75VSP PC262 10U_0805_6.3V6K 2 PC261 10U_0805_6.3V6K 20 VTT 18 19 VLDOIN VTTREF_1.5V +1.5VP C SYSON 1.5V_B+ PR159 0_0402_5% PR154 10.2K_0402_1% FB_1.5V +1.5VP PR160 10K_0402_1% PR158 887K_0402_1% PC162 1U_0402_16V7K VTTREF_1.5V off on on PC161 0.033U_0402_16V7K 10 +5VALW 2 PC160 1U_0603_10V6K PC156 680P_0402_50V7K 31 +0.75VSP off off on EN_1.5V Level L L H VDDQ @ 1 VDD TON_1.5V Mode S5 S3 S0 BOOT VTTREF +5VALW PQ152 FDMC7692S_MLP8-5 17 PR156 4.7_1206_5% GND RT8207MZQW_WQFN20_3X3 VDDP 21 FB 11 PAD VTTSNS S3 VDD_1.5V CS PU150 VTTGND PGND S5 PR157 5.1_0603_5% 12 PHASE 16 PC159 1U_0603_10V6K LGATE SNUB_+1.5VP PC152 + 390U_2.5V_M C 14 13 +1.5VP PR152 20K_0402_1% 2CS_1.5V PQ151 AON7408L PL152 1UH_FDSD0630-H-1R0M-P3_11A_20% 15 TON UGATE DL_1.5V PC260 10U_0805_6.3V6K SW_1.5V PGOOD @ DH_1.5V PC155 0.22U_0402_10V6K PC158 4.7U_0805_25V6-K PC157 10U_0805_25V6K PC154 2200P_0402_50V7K PC153 0.1U_0402_25V6 2.2_0402_5% @PC163 @ PC163 0.1U_0402_10V7K B 34 0.75VR_EN PJP152 31,34,39,40 SUSP# @PR161 @ PR161 0_0402_5% EN_0.75VSP Note: S3 - sleep ; S5 - power off B PR162 0_0402_5% 1 PAD-OPEN 4x4m PJP153 +1.5VP +1.5V (12A,480mils ,Via NO.= 24) PAD-OPEN 4x4m @ PC164 0.1U_0402_10V7K PJP76 +0.75VSP +0.75VS (1A,40mils ,Via NO.= 3) PAD-OPEN 3x3m A A Compal Secret Data Security Classification Issued Date 2010/07/20 Deciphered Date 2012/12/31 Title Compal Electronics, Inc PWR-1.5VP / +0.75VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Thursday, February 16, 2012 Date: Rev 0.2 SAMSUNG Sheet 38 of 48 PL401 HCB1608KF-121T30_0603 B+ D PR401 100K_0402_1% PC407 10U_0805_25V6K 2 D PC403 2200P_0402_50V7K 1 +3VS PC401 0.1U_0402_25V6 +1.05VSP_B+ PC408 10U_0805_25V6K 5 SW VFB V5IN TST DRVL UG_+1.05VSP SW_+1.05VSP UG_+1.05VSP1 11 PQ402 TPCA8059 2 +1.05VSP1 @ PR408 1.2K_0402_1% 2 C @ PC413 1000P_0402_50V7K +1.05VSP PR406 4.7_1206_5% PC410 1U_0603_10V6K PR407 470K_0402_1% @ PC411 0.1U_0402_16V7K PL402 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% +5VALW LG_+1.05VSP 1 TP BST_+1.05VSP +1.05VSP PR409 4.99K_0402_1% PC402 RF_+1.05VSP EN 10 + PC412 1U_0402_16V7K 330U_D2_2.5VY_R15M DRVH FB_+1.05VSP VBST TRIP C EN_+1.05VSP PGOOD PQ401 AON7518 PR404 0_0402_5% TRIP_+1.05VSP 1 PR402 60.4K_0402_1% 31,34,38,40 SUSP# PR405 PC405 2.2_0402_5% 0.22U_0402_10V6K BST1_+1.05VSP PU400 TPS51212DSCR_SON10_3X3 SNUB_+1.05VSP2 34,41 VCCP_PWRGOOD PC406 680P_0402_50V7K PR410 100_0402_1% VCCIO_SENSE VCCIO_SENSE1 PR414 10K_0402_1% PJP402 PAD-OPEN 4x4m PJP403 +1.05VSP B +1.05VS_VCCP(12A,480mils ,Via NO.= 24) B PAD-OPEN 4x4m A A Compal Secret Data Security Classification Issued Date 2010/07/20 Deciphered Date 2012/12/31 Title Compal Electronics, Inc PWR-V1.05SP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Thursday, February 16, 2012 Date: Rev 0.2 SAMSUNG Sheet 39 of 48 A B C D 1 PU180 SY8033BDBC_DFN10_3X3 2 @ 1 2 PR182 10K_0402_1% PC183 22U_0805_6.3V6M FB_1.8VSP PR181 20K_0402_1% PC182 22U_0805_6.3V6M +1.8VSP PC188 68P_0402_50V8J 1 SNUB_1.8VSP PR186 4.7_1206_5% NC 1 @ PR184 47K_0402_5% FB EN PC186 680P_0603_50V7K EN_1.8VSP LX SVIN 11 PR183 0_0402_5% LX_1.8VSP PC187 0.1U_0402_10V7K PG PVIN TP LX NC PC184 22U_0805_6.3V6M PVIN 10 VIN_1.8VSP 31,34,38,39 SUSP# PL182 1UH_NRS4018T1R0NDGJ_3.2A_30% PL181 HCB1608KF-121T30_0603 +5VALW PJP182 +1.8VSP +1.8VS (3A,120mils ,Via NO.= 6) PAD-OPEN 4x4m 3 4 Compal Secret Data Security Classification Issued Date 2009/01/23 Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Compal Electronics, Inc PWR-1.8VSP Document Number Rev 0.2 SAMSUNG Thursday, February 16, 2012 D Sheet 40 of 48 The 1k PD on the VCCSA VIDs are empty These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability VID [0] 0 1 D VID[1] 1 VCCSA Vout 0.9V 0.8V 0.725V 0.675V D output voltage adjustable network SNUB_+VCCSA +VCC_SAP TDC 4.2A Peak Current 6A OCP current 7.2A PR801 4.7_1206_5% PC805 680P_0402_50V7K PU801 SY8037BDCC_DFN12_3X3 12 PVIN LX FB PG VOUT VID1 EN VID0 SA_PGOOD 31 PR804 100K_0402_5% +VCCSAP +3VS +VCCSA_EN PR802 1K_0402_5% 2 PR806 0_0402_5% 34,39 PC804 22U_0805_6.3V6M LX PC803 22U_0805_6.3V6M LX SVIN PC802 22U_0805_6.3V6M PVIN PC801 22U_0805_6.3V6M 2 +VCCSAP_FB 10 13 PC820 22U_0805_6.3V6M 1 PC819 22U_0805_6.3V6M 2 PC817 0.1U_0603_25V7K C PC818 2200P_0402_50V7K PC815 68P_0402_50V8J PL801 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% +VCCSA_PHASE 2 11 PC809 0.1U_0402_10V7K +VCCSA_PWR_SRC PR805 1K_0402_5% PL803 HCB1608KF-121T30_0603 GND +5VALW C PR812 100_0402_5% VCCP_PWRGOOD @ PR811 0_0402_5% H_VCCSA_VID0 H_VCCSA_VID1 PJP801 +VCCSAP B +VCCSA_SENSE +VCCSA B PAD-OPEN 4x4m A A Compal Secret Data Security Classification Issued Date 2010/07/20 Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc PWR-VCC_SAP Document Number Rev 0.2 SAMSUNG Thursday, February 16, 2012 Sheet 41 of 48 @ PR508 1 NTC_PH203 2P: install 1P: @ @ PR514 0_0402_5% PAD VSNA VSPA DIFFA TRBSTA# FBA COMPA IOUTA ILIMA DROOPA CSCOMPA CSSUMA CSREFA CSP2A CSP1A TSNSA NCP6132BMNR2G_QFN60_7X7 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PWMA BSTA HGA SWA LGA BST2 HG2 SW2 LG2 PVCC PGND LG1 SW1 HG1 BST1 1 PR523 BST3 BST2 6132P_VCCP 43 LG3 HG2 43 PR525 BST2_1 4.7_0603_5% 43 LG2 43 0_0402_5% PR530 BST1 LG1 43 HG1 43 806_0402_1% DROOP CSREF 1000P_0402_50V7K CSP2A 43 +5VS CSP1 @ PR553 0_0402_5% CSREF 1500P_0402_50V7K @ PC537 330P_0402_50V7K PR557 75K_0402_1% PC525 0.047U_0402_16V7K 1 CSREF @PR537 @ PR537 0_0402_5% SWN3 43 3P: install 2P: @ PR544 5.76K_0402_1% PR558 165K_0402_1% 3Phase: @ 2Phase: install CSP3 B TSENSE SWN2 43 SWN1 43 PC530 0.047U_0402_16V7K PR549 5.76K_0402_1% PR550 PC532 1000P_0402_50V7K PC535 PR539 5.76K_0402_1% 43 SW1 2Phase: @ 1Phase: install @PR531 @ PR531 0_0402_5% 2 CSREF C PC533 0.047U_0402_16V7K CSP3 @ PR542 0_0402_5% CSREF +5VS Option for phase GFX 43 PR554 160K_0603_1% SWN1 PR556 160K_0603_1% SWN2 PR559 160K_0603_1% SWN3 PC536 PC538 43 Option for phase CPU @ PR546 0_0402_5% 1U_0402_16V7K SW2 PC522 0.22U_0402_10V6K DRVEN CSSUM PR555 PR560 43 6132_PWM 43 PR541 806_0402_1% 2.2U_0603_10V7K 0_0402_5% PC520 BST1_1 100K_0402_1%_TSM0B104F4251RZ +5VS SW3 3P: 73.2K 2P: 41.2K PR536 73.2K_0402_1% PC526 CSCOMP PR547 PC529 1COMP_CPU1 6.04K_0402_1% 2200P_0402_50V7K PH504 PUT CLOSE TO V_GT HOT SPOT PC519 0.22U_0402_10V6K PR532 PR533 4.7_0603_5% 1U_0402_16V7K CSP1 CSP2 CSP3 122P_0402_50V8J 23.7K_0402_1% 0.033U_0402_16V7K PR545 PC528 2FB_CPU1 PR548 PC531 49.9_0402_1% 2FB_CPU3 680P_0402_50V7K 10_0402_1% 0.033U_0402_16V7K PR551 PR552 2 FB_CPU2 43 2 HG3 CSP2 CSCOMP SWN2A PC518 0.22U_0402_10V6K PC527 BST3_1 4.7_0603_5% 2 1K_0402_1% PC534 43 2P: 36K 1P: 26.1K PR543 8.06K_0402_1% PR519 5.49K_0402_1% VSN PC524 1000P_0402_50V7K VSP B TRBST# SWN1A 2P: install 1P: @ 6132_PWMA 43 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TRBST# FB_CPU COMP_CPU IMON ILIM_CPU DROOP 21K_0402_1% 0_0402_5% VCCSENSE 1 VCC VDDBP VRDYA EN SDIO ALERT# SCLK VBOOT ROSC VRMP VRHOT# VRDY VSN VSP DIFF PR538 0_0402_5% VSSSENSE 2 CSP2A CSP1A TSENSEA PR520 36K_0402_1% PR540 1U_0402_16V7K VGATE 18,31 VR_HOT# CSP2A PC514 0.047U_0402_16V7K PR535 10K_0402_5% 31 TSENSEA 5.49K_0402_1% PH502 100K_0402_1%_TSM0B104F4251RZ PR529 1K_0402_1% PR534 75_0402_1% @ PR518 0_0402_5% PC515 TSENSE PR528 95.3K_0402_1% 1 CPU_B+ VR_ON_CPU VR_SVID_DAT1 PR526 VR_SVID_ALRT# 10K_0402_1% VR_SVID_CLK VBOOT ROSC_CPU 10 VRMP 11 VR_HOT# 12 VGATE 13 14 15 DIFF_CPU PC523 47P_0402_50V8J VR_ON +3VS +1.05VS_VCCP 2VR_SVID_DAT1 0_0402_5% 1PR516 21.5K_0402_1% CSCOMPA DIFFA TRBSTA# FBA COMPA IMONA ILIMA DROOPA PR527 TRBST# FB COMP IOUT ILIM DROOP CSCOMP CSSUM CSREF CSP3 CSP2 CSP1 TSNS DRVEN PWM 6132_VCC PR521 0_0402_5% PC521 0.01U_0402_25V7K 2 PR522 54.9_0402_1% VR_SVID_DAT VR_SVID_ALRT# VR_SVID_CLK 130_0402_1% PR524 2 PC501 2.2U_0603_10V7K 31 PR515 PU500 C PC516 1U_0402_16V7K CSREFA 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 PR501 2_0603_5% +5VS +1.05VS_VCCP PC511 0.047U_0402_16V7K PC512 1000P_0402_50V7K CSREFA 43 CSSUMA VSS_AXG_SENSE CSP1A CSREFA SWN1A SWN2A 80.6K_0603_1% PC513 1000P_0402_50V7K CSREFA 1000P_0402_50V7K 2 80.6K_0603_1% PR513 VCC_AXG_SENSE DROOPA 1 PR512 PC510 2200P_0402_25V7K COMPA1 2 5.11K_0402_1% 1 HF: 1.65K 2P: 1.65K 1P: 1K PR511 PR510 1K_0402_1% 1.65K_0402_1% 165K_0402_1% PC517 1U_0402_16V7K CSCOMPA 10P_0402_50V8J 1 PR517 PC509 PC506 13.7K_0402_1% PC508 680P_0402_50V7K FBA2 PR507 13.7K_0402_1% PR509 10_0402_1% 2 PC507 0.033U_0402_16V7K D PH503 220K_0402_5%_ERTJ0EV224J 2 PR505 24K_0402_1% PR506 75K_0402_1% PR504 806_0402_1% FBA1 PC504 PR503 8.06K_0402_1% 2 D TRBSTA# PUT CLOSE TO GT Inductor PC503 1U_0402_16V7K 560P_0402_50V7K PC502 3300P_0402_50V7K FBA3 1500P_0402_50V7K PR502 10_0402_1% PC505 PUT CLOSE TO VCORE HOT SPOT PH501 220K_0402_5%_ERTJ0EV224J A A PUT CLOSE TO VCORE Phase Inductor Compal Secret Data Security Classification Issued Date 2009/12/01 2010/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR-CPU_CORE Size Document Number Custom Date: Rev 0.2 QCL70 Thursday, February 16, 2012 Sheet 42 of 48 PC545 0.1U_0402_25V6 PC546 2200P_0402_25V7K D CSREF 42 42 LG2 PQ504 TPCA8057 10_0402_1% PC547 SWN1 42 B+ PL516 HCB2012KF-121T50_0805 PR566 V2N_CPU SNUB_CPU2 V1N_CPU 3 PQ502 TPCA8057 PR564 4.7_1206_5% PR565 1SNUB_CPU1 LG1 PC544 10U_0805_25V6K PQ507 AON7518 SW2 +CPU_CORE PL512 0.36UH_FDUE1030D-H-R36M=P3_32A_20% 42 @ PR563 4.7_1206_5% 42 PC543 10U_0805_25V6K PQ505 AON7518 5 SW1 HG2 3 42 +CPU_CORE PL511 0.36UH_FDUE1030D-H-R36M=P3_32A_20% 42 PC541 2200P_0402_25V7K PC542 0.1U_0402_25V6 PC540 10U_0805_25V6K PC539 10U_0805_25V6K @ D CPU_B+ HG1 PQ503 AON7518 42 PQ501 AON7518 CPU_B+ CSREF 10_0402_1% SWN2 42 680P_0402_50V7K CPU_B+ 680P_0402_50V7K HG3 PL513 0.36UH_FDUE1030D-H-R36M=P3_32A_20% SW3 + + 2 CPU_B+ @ PC555 100U_25V_M QC 45W CPU VID1=0.9V IccMax=94A Icc_Dyn=66A Icc_TDC=56A R_LL=1.9m ohm OCP~110A +CPU_CORE 3 @ 42 1 PC552 2200P_0402_25V7K PC551 0.1U_0402_25V6 PC550 10U_0805_25V6K PC549 10U_0805_25V6K PC554 100U_25V_M PQ511 AON7518 42 C PQ509 AON7518 PL517 HCB2012KF-121T50_0805 @ PC553 0.1U_0603_25V7K QC 45W CPU (HF) solution: 3+2 MOS: cpu_core > Gfx_core > DC 35W CPU VID1=1.05V IccMax=53A Icc_Dyn=43A Icc_TDC=33A R_LL=1.9m ohm OCP~65A QC 45W CPU solution: 3+2 MOS: cpu_core > Gfx_core > 上 下1(FDMS0308AS) 上2(AON7518) 2(AON7518)下1(FDMS0308AS) C 上 下1(FDMS0308AS) 上1(AON7518) 1(AON7518)下1(FDMS0308AS) PR568 4.7_1206_5% PC548 PQ506 TPCA8057 SNUB_CPU3 LG3 V3N_CPU PR5691 DC 35W CPU solution: 2+1 MOS: cpu_core > Gfx_core > CSREF 10_0402_1% 42 PC556 SWN3 42 680P_0402_50V7K 上 下1(FDMS0308AS) 上1(AON7518) 1(AON7518)下1(FDMS0308AS) CPU_B+ +5VS PR580 4.7_1206_5% PQ508 TPCA8057 PR581 2 PR577 1EN_GFX2 2K_0402_1% 1VCC_GFX2 PR578 PR579 0_0402_5% 0_0402_5% CSREFA 42 10_0402_1% PC568 PWM EN VCC DRVH SW GND DRVL PC561 2200P_0402_25V7K PC560 0.1U_0402_25V6 PQ519 AON7518 +GFX_CORE HG2A SW2A @ FLAG PL515 FDUM0640J-H-R36M=P3 PR582 4.7_1206_5% NCP5911MNTBG_DFN8_2X2 PC570 2.2U_0603_10V7K LG2A PQ510 TPCA8057 SWN1A 42 PR584 0_0402_5% 680P_0402_50V7K BST 5 PQ517 AON7518 PC565 2200P_0402_25V7K PC564 0.1U_0402_25V6 PC563 10U_0805_25V6K PQ515 AON7518 PC562 10U_0805_25V6K 6132_PWM DRVEN LG1A NCP5911MNTBG_DFN8_2X2 PC567 2.2U_0603_10V7K 42 PU502 PL514 FDUM0640J-H-R36M=P3 2 GND DRVL SW1A CSREFA PR583 10_0402_1% SNUB_GFX2 VCC SW HG1A PC566 0.22U_0402_10V6K EN BSTA2_1 DRVH FLAG PWM +GFX_CORE BST PR571 4.7_0603_5% 1SNUB_GFX1 2 1EN_GFX1 DRVEN 2K_0402_1% 1VCC_GFX1 PR575 PR576 0_0402_5% 0_0402_5% +5VS @ BSTA2 PR573 42 6132_PWMA PQ513 AON7518 PU501 1 BSTA1_1 PC557 B PC558 10U_0805_25V6K 1 4.7_0603_5% 0.22U_0402_10V6K BSTA1 42 2Phase: install 1Phase:: @ PR570 PC559 10U_0805_25V6K CPU_B+ B SWN2A 42 PR585 0_0402_5% PC569 680P_0402_50V7K A A QC 45W GT2 VID1=1.23V IccMax=46A Icc_Dyn=37A Icc_TDC=38A R_LL=3.9m ohm OCP~55A DC 35W GT2 VID1=1.23V IccMax=33A Icc_Dyn=20.2A Icc_TDC=21.5A R_LL=3.9m ohm OCP~40A Compal Secret Data Security Classification Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc PWR-CPU_CORE Document Number Rev 0.2 QCL70 Thursday, February 16, 2012 Sheet 43 of 48 +CPU_CORE 1 Below is 458544_CRV_PDDG_0.5 Table 5-8 +GFX_CORE PC1105 10U_0805_6.3V6M PC1104 10U_0805_6.3V6M PC1103 10U_0805_6.3V6M PC1102 10U_0805_6.3V6M PC1101 10U_0805_6.3V6M +GFX_CORE 1 1 +CPU_CORE Socket Bottom x 22 µF (0805) x (0805) no-stuff sites Socket Top x 22 µF (0805) x (0805) no-stuff sites D D 2 2 2 2 2 1 1 2 PC1121 22U_0805_6.3V6M PC1122 22U_0805_6.3V6M PC1123 22U_0805_6.3V6M PC1124 22U_0805_6.3V6M PC1125 22U_0805_6.3V6M + PC1126 22U_0805_6.3V6M PC1127 330U_D2_2V_Y + PC1128 330U_D2_2V_Y + PC1129 330U_D2_2V_Y + + 2 + PC765 PC763 C 1 330U_D2_2V_Y +CPU_CORE PC762 PC1120 22U_0805_6.3V6M 330U_D2_2V_Y 22U_0805_6.3V6M PC1119 22U_0805_6.3V6M PC761 22U_0805_6.3V6M 2 PC760 22U_0805_6.3V6M + PC759 22U_0805_6.3V6M + PC758 22U_0805_6.3V6M + PC757 22U_0805_6.3V6M 1 PC756 22U_0805_6.3V6M 2 1 PC755 22U_0805_6.3V6M PC1118 22U_0805_6.3V6M 1 PC754 22U_0805_6.3V6M 1 PC753 22U_0805_6.3V6M PC1117 22U_0805_6.3V6M +1.05VS_VCCP PC752 22U_0805_6.3V6M PC1115 22U_0805_6.3V6M PC1166 PC1116 22U_0805_6.3V6M PC1165 2 330U_D2_2V_Y PC1114 22U_0805_6.3V6M PC1164 2 330U_D2_2V_Y PC1113 22U_0805_6.3V6M 330U_D2_2V_Y PC1162 22U_0805_6.3V6M PC1112 22U_0805_6.3V6M PC1161 22U_0805_6.3V6M PC1160 22U_0805_6.3V6M PC1111 22U_0805_6.3V6M PC1159 22U_0805_6.3V6M 2 PC751 22U_0805_6.3V6M PC1158 22U_0805_6.3V6M +CPU_CORE PC1157 22U_0805_6.3V6M PC1156 22U_0805_6.3V6M PC1110 10U_0805_6.3V6M PC1155 22U_0805_6.3V6M PC1109 10U_0805_6.3V6M PC1154 22U_0805_6.3V6M PC1108 10U_0805_6.3V6M PC1153 22U_0805_6.3V6M PC1107 10U_0805_6.3V6M PC1152 22U_0805_6.3V6M PC1106 10U_0805_6.3V6M PC1151 22U_0805_6.3V6M C PC1130 330U_D2_2V_Y + PC1131 330U_D2_2V_Y Chief River B 330uF*9m 8layer for DC CPU 470uF*4.5m 22uF 10uF 16 10 8layer for QC CPU 16 10 6layer for DC CPU 16 10 6layer for QC CPU 16 10 GFX_CORE DC 12 GFX_CORE QC 12 1.05V_VCCP 12 B A A Compal Secret Data Security Classification 2008/09/15 Issued Date Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc PWR - PROCESSOR DECOUPLING Document Number Rev 0.2 QCLA4 LA-8861P M/B Thursday, February 16, 2012 Sheet 44 of 48 NO DATE PAGE MODIFICATION LIST PURPOSE -1 10 11 12 13 14 15 16 17 18 19 20 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 2011/09/29 P51-PWR_+3VALWP/+5VALWP P53-PWR_ +1.05VS_VCCP/+16VSP P54-PWR_+VCCSAP/1.8VSP P57-PWR +CPU_CORE DECOUPLING P53-PWR_ +1.05VS_VCCP/+16VSP P49-PWR_BATTERY CONN / OTP P57-PWR +CPU_CORE DECOUPLING P57-PWR +CPU_CORE DECOUPLING P57-PWR +CPU_CORE DECOUPLING P57-PWR +CPU_CORE DECOUPLING P57-PWR +CPU_CORE DECOUPLING P57-PWR +CPU_CORE DECOUPLING P57-PWR +CPU_CORE DECOUPLING P57-PWR +CPU_CORE DECOUPLING P57-PWR +CPU_CORE DECOUPLING P49-PWR_BATTERY CONN / OTP P51-PWR_+3VALWP/+5VALWP P49-PWR_BATTERY CONN / OTP P51-PWR_+3VALWP/+5VALWP Change PU330 to RT8205L Change PU400 to RT8237C Change PU450 to SY8037B Change HMOS to MDV1525 Change HMOS to MDV1525 Change PD5,PD6 to SCA00001G00 Change PR589 from 348 to 8.06k Change PR590 from 3.65k to 806 Change PC574 from 680P to 0.033u Change PC577 from 4700P to 0.033u Change PR548 from 1.21k to 8.06k Change PR550 from 10.7k to 806 Change PC547 from 680P to 0.033u Change PC551 from 4700P to 0.033u Add snubber and boost resistor Add PR22 30k,PR27 100k, PR32 Ohm Change PC360 to SE000006R80 Add PR17 14k, PR33 Ohm Add PR373 Ohm Change source Change source Change source Change source Change source ESD team request FAE suggestion FAE suggestion FAE suggestion FAE suggestion FAE suggestion FAE suggestion FAE suggestion FAE suggestion For 3x3 H-MOS solution For 120W adapter protect(9012) Change source For CPU temperature protect(9012) For 3/5V always power on(9012) Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/11/11 Deciphered Date 2011/11/11 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Power PIR Thursday, February 16, 2012 Rev 0.2 QFKAA Sheet 45 of 48 HW PIR (Product Improve Record) D C B A QCLA4,5 LA-7201P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.0 TO 0.1 GERBER-OUT DATE: 2011/12/30 NO DATE PAGE MODIFICATION LIST PURPOSE 11/24 33 Change P33 ALC280 schematic to ALC259 schematic For audio function 11/24 34 Change JEXMIC.4 JACK_SENSE to MIC_SENSE For audio function 11/24 35 Delete UB3,RB26,CB18,RH296 For delete CIR function 11/24 6,13,21 Delete QC1,RC4,C261,U17,R147,R103,R360,R392,R390,R1441~1442,R361,R106,RH304 For LVDS only 11/24 6,13,17 Delete Q23,C293,R62,R389,R120,R79,R97,L60,R262~265,R299~300,RH275,R1440 For LVDS only 11/24 6,13 Delete CPU_EDP_HPD,+LCD_VDD_R,+PANEL_VDD,LVDS_ENVDD,+3VS_LVDSDDC For LVDS only 11/24 13 Delete D15 BOM structure and JLVDS.10 connect to +3VS For LVDS function 11/24 13 Add J17 connector and change JLVDS from 40 to 30 pin connector For LVDS function 11/24 20 Delete USB20_N13,USB20_P13 For no Glasses free 3D Panel 10 11/24 13 Change RC82 BOM structure from IEDP@ to @ For LVDS function 11 11/24 5,17 Change RC157,RC158,RH119,RH203 BOM structure from LVDS@ to mount For LVDS function 12 11/24 17 Delete CLK_CPU_EDP#,CLK_CPU_EDP For LVDS only 13 11/24 15 Delete CEC schematic and JHDMI.13 HDMI_CEC net For no CEC support 14 11/24 15 Delete R570,D55 and change U9.4 HDMI_HPD_R to HDMI_HPD For HDMI HPD 15 11/25 15 Change L8~11 to SM070001U00 For HDMI signal 16 11/25 15 Delete U9.5 from +5VL to +5VS For HDMI HPD 17 11/25 33 Change Audio codec schematic For ALC259-VC2 18 11/25 17,29 Delete CH16,CH18,card reader schematic For RTS5129 19 11/25 26 Delete FP & B-CAS schematic For no support FP & B-CAS function 20 11/25 35,37 Delete JFUN,R8,R1466~1467,D90 For no support JFUN 21 11/25 20,27 Delete USB20_N10,USB20_P10,USB20_N12,USB20_P12 For no support TV tuner & 3G 22 11/25 27 Delete RH181 & 3G,B-CAS,JET schematic For no support TV tuner & 3G 23 11/25 16,27 Delete mSATA schematic For no support mSATA function 24 11/25 27 Delete RCL3,271@ component and net OSC_IN_R_R,OSC_IN_R For no support S&M function 25 11/25 Change RC3 from 1Kohm to 10Kohm (SD028100280) For no support eDP function 26 11/25 35 Delete UB1.89 HDPACT,UB1.86 HDPLOCK,UB1.68 HDPINT For no support G-SENSOR function 27 11/28 35 Change PCH_PWR_EN from UB1.70 to UB1.68 and add UB1.70 EN_DFAN1 For support RPM FAN 28 11/28 5,35 Delete C1~4,R1~2,D1 and UB1.26 FANPWM For no support PWM FAN 29 11/29 25 Delete S&C schematic For no support S&C 30 11/29 31,32 Delete USB3.0 Host schematic For no support external USB3.0 host IC 31 11/30 38 change R409 from 120K_1% to 120K_5% For change tolerance 32 11/30 33 change RA17 from 0_1% to 0_5% For change tolerance 33 11/30 13 Delete R260 and short directly For reduce circuit 34 12/01 16 change DH1 from @ to NOGCLK@ For BOM control 35 12/01 37 Add SW4 For Debug 36 12/01 36 Delete U21,C453,C452 For LID on small board 37 12/02 35 Delete CPSETIN For delete EC930 schematic 38 12/02 16 Add JRTC,CH9,DH8,DH9,R227 For non-rechargeable RTC schematic 39 12/02 36 Delete JBLG schematic For non-keyboard led schematic 40 12/05 36 Modify JKB pin define For meet SS KB Matrix 41 12/05 13 Change location from J17 to JLVDS1 For location naming 42 12/06 35 Delete UB1.85 SM_SENSE# For no support S&M 43 12/06 25 Modify JUSIO pin define For small board connect 44 12/06 38 Delete R425 and 0.75VR_EN# For Power circuit connect 45 12/07 25 Add JODDB For 15" ODD connector 46 12/07 15 Change U9.5 connect from +5VS to +HDMI_5V_OUT For prevent leakage issue 47 12/08 29 Change JCRIO pin define For small board connect 48 12/12 21 Change UH1.K1 and RH180.2 from BT_ON# to PCH_GPIO34 For common GPIO pins on EC side 49 12/12 35 UB1.18 and RB11 connect to BT_ON# For common GPIO pins on EC side 50 12/12 25,35,37 Delete PWR_ON_LED# net For common GPIO pins on EC side 51 12/12 25 Change JUSIO pin define For LED behavior 52 12/12 16 Delete CH9,DH8,DH9,R277,JRTC For RTC change to rechargeable 53 12/13 21 Delete Q51 and change PCH_WL_BT_LED to PCH_GPIO69 For change WL_BT_LED# to EC GPIO 54 12/13 35 UB1.21 connect WL_BT_LED# For change WL_BT_LED# to EC GPIO 55 12/13 37 Change Q156B.3 from WL_BT_LED# to WIMAX_LED# and connect to R802 For WLAN LED behavior 56 12/13 35 Delete UB1.127 (USB_OC#0) and UB1.17 (USB_OC#1) For no support USB S&C 57 12/13 20,29 Add TPM schematic For TPM function 58 12/13 27 Delete Q36 For change BT_ON# to EC GPIO 59 12/13 14,30,37 Change JCRT,JUSBA,JUSBB,JTP symbol For connector list update 60 12/13 25,29 Change JUSIO,JCRIO symbol For connector list update 61 12/14 27 Change UCL1 to SLG3NB244VTR For green clock 62 12/14 29 Change UT1.5 and RT7.1 net from +3VALW to +3VALW_PCH For ErP Lot6 function 63 12/14 21 Add RH181 and connect ISDBT_DET, delete RH297 For no support TV tuner 64 12/14 21 Change RH194 from 100K 5% to 10K 5% For update resistor value 65 12/14 21 Change RH315.2 connect +3VS and BOM structure to mount For update resistor value 66 12/14 37 Change ZZZ P/N to DA60000T600 For update PCB P/N 67 12/14 37 Move D89 to TP small board For Move to TP small board 68 12/15 16~24 Change UH1 P/N to SA00005FH30 For update UH1 P/N 69 12/15 30 Change CR40 P/N to SF000002Y00 For layout limitation 70 12/15 33 Delete RA53 For common design 71 12/15 25 Delete C381~4 For placement update 72 12/15 30 Delete RR23~24,CR26,RR36~37,CR29 For connect GND directly 73 12/15 Delete CC67 For not reserve 74 12/19 16 Delete T67~T69 For not reserve 75 12/19 29 Change YT1 form SJ132P7KW10 to SJ100004Z00 (small package) For change to small size 76 12/19 29 Change CT2, CT3, CT4, CT5 from SE095104K80 to SE102104K00 For BOM reduce 77 12/19 29 Change JCRIO to SP010015H00 For follow connector list 78 12/20 13 Delete JLVDS.28 (+LCD_INV) For prevent issue 79 12/20 37 Modify H1~H17 For Update screw hole D C B A Compal Electronics, Inc Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC HW-PIR Rev 0.2 QCLA4,5 LA-8862P M/B Date: Thursday, February 16, 2012 Sheet 46 of 48 HW PIR (Product Improve Record) D C B A QCLA4,5 LA-8862P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.0 TO 0.1 GERBER-OUT DATE: 2011/12/30 NO DATE PAGE MODIFICATION LIST PURPOSE 80 12/20 35 Change UB1.68 (PCH_PWR_EN) to UB1.107 For EC common 81 12/20 35 Change UB1.73 (UMA_ENBKL) to UB1.76 For Update screw hole 82 12/20 21 Change RH198 from 100k to 10k For follow Intel checklist 83 12/20 05 Change UC1.5 from +3VALW to +3VALW_PCH For design change 84 12/20 16 Modify SATA_LED# to10k (RH29) +5VS pull high & 20k (RH35) pull low For design change 85 12/20 17 Change CLKREQ_CR#,CLKREQ_USBA30#,CLKREQ_USB30# to PCH_GPIO25, 26, 44 For design change 86 12/20 20,23 Change CH104 to 100p and CH71 to 0402 For design change 87 12/20 27,35 Change BT_ON# netname to BT_ON and UA4 to UM4 For design change 88 12/20 27 Modify LED_WIMAX# to 100k +5VS pull high & 200k pull low For design change 89 12/20 35 Delete CB13 For design change 90 12/20 33 Change CA3,CA46,CA36 to 0805_6.3V6M For cost down 91 12/20 38 Delete R5534 and short directly For design change 92 12/20 37 Changr R819 from +5VS to +3VS For design change 93 12/20 5,25 Changr C13,C17,C356,C355,C354 to 0805_6.3V6M and unmount C354 For cost down 94 12/20 35 Delete UB2,CB17,RB25 and connect UB1.127 to PM_SLP_S4#, UB1.14 to PM_SLP_S5# For cost down 95 12/20 35 Delete RB24,RB28,RB4,RB5,RB7,R37 and change UB1.119,117,75,64,27,16 to NC For cost down 96 12/21 28 Change symbol from SP021105131 For apply symbol 97 12/21 35 Change TP_CLK,TP_DATA pull high to +5VS For TP spec 98 12/21 13 Unmount D84 For reserve 99 12/22 15,25,30 Swap L9,L11,LR1,LR2,L53,L54 signal For swap signal 100 12/22 30 Swap U3TXDP1_R_L and U3TXDN1_R_L, swap U3RXDP1_R_L and U3RXDN1_R_L For swap signal 101 12/23 14,15 Change F1,F2 to SP040003A00 For component common 102 12/24 29 Change RR66~67 to mount, LR9 to unmount For choke reserved 103 12/24 37 Cancel H6, H17 (FAN stand-off) and change H4 to H_3P3 (VGA) For ME drawing update 104 12/24 28 Change PJ29 from JUMP_43X118 to JUMP_43X39 For layout concern 105 12/24 38 Delete R105, add PJ30 to contact +3VS & +3V_WLAN For no support AOAC function 106 12/26 36 Update JDB symbol and modify pin define For connector list update and pin define for customer's request 107 12/26 13,17 Delete RH282, change RH116 to mount, JLVDS1.2 contact LVDS_SEL For update pin define and BOM reduce 108 12/26 13 JLVDS1.1&11&12 contact GND For LVDS cable smooth route and BOM reduce 109 12/26 33 Move RA32 & RA33 to Audio/B For AMIC function 110 12/26 29 JCRIO.11 contact SENSE_A, JCRIO.12 contact INT_MIC For AMIC function 111 12/26 36 Swap JKB connector pin define For latest keyboard spec 112 12/26 29 Swap LR9 pin define For layout concern 113 12/27 29 Swap JCRIO pin define For layout concern 114 12/27 37 Update JTP pin define For PIN define rule 115 12/27 29 Update TPM schematic For co-lay SLB9635 and SLB9655 116 12/27 28 Add CL35 and un-mount For EMI request 117 12/27 21 Change CIR_EN# to PCH_GPIO39 and ISDBT_DET to PCH_GPIO48 For schematic update 118 12/27 21 Change HDD2_DET# to PCH_GPIO57 and LNB_EN to PCH_GPIO70 For schematic update 119 12/27 21 Change 3D_DET# to PCH_GPIO71 For schematic update 120 12/27 20,30,35 Add S&C schematic For reserve S&C schematic 121 12/27 33 Add Analog MIC schematic For Analog MIC 122 12/27 28 Change RL8.2 from LAN_X1 to LAN_X2 For vendor recommendation 123 12/27 11,21 Add D54,RH210,RH100,QC9 and delete RC117,RC118 For Ivy/Sandy bridge M1/M3 co-lay solution 124 12/27 11 Change QC7,QC8 to always mount For Ivy/Sandy bridge M1/M3 co-lay solution 125 12/27 38 Change R158 from 100Kohm to 220Kohm For intel S3 power reduce sequence between +1.5VS_CPU and +0.75VS 126 12/27 33 Add CA64 0402 cap @ on SENSE_A For audio sense A pin 127 12/28 30 Change R569 to PJ31 For S&C function 128 12/28 30 Add RH4,CH80 For prevent abnormal turn on 129 12/28 30 Add CH99,CH102 and delete CH97 For prevent abnormal turn on and soft start 130 12/29 38 Change R5545 from 100k to 10k For prevent abnormal turn on and soft start 131 01/03 28 Change UL3,UL4 from SP050006N00 to SP050005Z00 For update transformer P/N 132 01/03 29 change UT1 P/N from SA00000GG40 to SA00000GG60 For TPM firmware update 133 01/03 27 change R1456,R1457,C907,C908,Q210 to @ For TPM firmware update QCLA4,5 LA-8862P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 TO 0.2 GERBER-OUT DATE: 2012/01/10 NO DATE PAGE MODIFICATION LIST PURPOSE 02/01 28 Add PJ32 and connect +3VALW_PCH & +3V_LAN For power saving 02/02 29 Change JCRIO.2 to connect MIC_SENSE and JCRIO.1 to connect NBA_PLUG For change pin define 02/02 33 Delete sense_A off page,CA64 and add RA32,RA33 For sense A circuit 02/02 37 Change JTP from SP010015H00 to SP01001BF10 For connector list 02/02 33 Add JMIC connector SP02000RO00 For connector list 02/02 27 Change JWLAN from SP07000JP00 to SP07000TB00 For connector list 02/02 38 Change Q44A to Q6B and delete Q44 For component reduce 02/02 16 Delete T67~69 For common design 02/03 35 UB1.38 connect AOAC_WLAN_PWR_EN# and UB1.91 connect WLAN_RST# For WLAN Power on/off and WLAN 10 02/03 27 Change R1456,R1457,C907,C908,Q210 to mount For WLAN Power on/off and WLAN 11 02/03 27 change R1457.1 to connect AOAC_WLAN_PWR_EN# For WLAN Power on/off and WLAN 12 02/03 27 Change JWLAN.22 to connect WLAN_RST#_R For WLAN Power on/off and WLAN 13 02/03 27 Change C260,CM7,CM8,CM9,C254 to connect +1.5VS_WLAN For WLAN Power on/off and WLAN 14 02/03 27 ADD PJ33 (PJ33 don't short),UM5,RM19,RM21 and +1.5VS_WLAN (power) For WLAN Power on/off and WLAN 15 02/03 27 Change UM4.1 to connect AOAC_WLAN_PWR_EN# For WLAN Power on/off and WLAN 16 02/06 28 Change CL63 from SE120102K80 to SE120102K90 For sourcer suggestion 17 02/06 37 Change H18,H19 to H_3P0N For ME drawing update 18 02/08 21 Change UH1.T7 from HDMI_HPD to CHP3_SERDBG For Eureka Serial POST GPIO 19 02/08 21 Change RH292 from 10Kohm to 1Kohm and delete T66 For Eureka Serial POST GPIO 20 02/08 21 Change UH1.T7 from HDMI_HPD to CHP3_SERDBG and connect to JCRT.4 For Eureka Serial POST GPIO 2010/09/03 Issued Date Deciphered Date C B reset reset reset reset reset reset reset A Compal Electronics, Inc Compal Secret Data Security Classification D 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC HW-PIR Rev 0.2 QCLA4,5 LA-8862P M/B Date: Thursday, February 16, 2012 Sheet 47 of 48 D QCLA4,5 LA-8862P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 TO 0.2 GERBER-OUT DATE: 2012/01/10 NO DATE PAGE MODIFICATION LIST PURPOSE 21 02/08 27 Add TL1 test point For LAN FAE suggestion 22 02/09 15 Add D94~D96 on HDMI signal For ESD request 23 02/09 27 Add D99,D100 on LAN signal For ESD request 24 02/09 14 DEL D3~D5 and add D97,D98 on CRT signal For ESD request 25 02/09 7,31 Add RC74 and net DRAMRST_CNTRL_EC connect RC74.1 & UB1.89 For DS3 function reserve 26 02/09 25 Add R79~82 For reduce SATA signals reflection 27 02/14 11 Change CD7 from SF000002O00 (H=5.9) to SF000002Z00 (H=4.4) For thermal issue D C C B B A A Compal Electronics, Inc Compal Secret Data Security Classification 2010/09/03 Issued Date Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC HW-PIR Rev 0.2 QCLA4,5 LA-8862P M/B Date: Thursday, February 16, 2012 Sheet 48 of 48 ... VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149... 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181... 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181