A B C D E 1 Compal confidential Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic 2 2009-07-15 Blade 1.4 MV 3 4 Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc Cover Sheet Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet E of 45 A B C Compal confidential D E Montevina Consumer 14" UMA CK505 Mobile Penryn Thermal Sensor EMC1402 72QFN Clock Generator SLG8SP553V P06 P17 uFCPGA-478 CPU P6, 7, Fan conn P06 H_A#(3 35) FSB H_D#(0 63) LVDS Panel Interface CRT P19 DDR3 SO-DIMM X2 BANK 0, 1, 2, Dual Channel USB conn x1 P9,10, 11, 12, 13, 14 USB2.0 X12 C-Link BT Conn USB Camera PCI-E BUS*5 Azalia Intel ICH9-M RTL8103EL (10/100M) Mini-Card Mini-Card TV-tuner or Robson WLAN P25 P30 P35 DMI X4 PCIE CardReader JMB385 P27 P15, 16 FCBGA 1329 Support V1.3 DDR3 800/1066MHz 1.5V Intel Cantiga MCH P18 HDMI 667/800/1066 MHz 1.05V P26 P26 SATA Master-1 mBGA-676 New Card Finger print SATA Slave P30 P19 P30 SATA Slave P20,21,22,23 Audio CKT P26 AMP & Audio Jack Codec_IDT9271B7 TPA6017A2 P28 in1 Slot RJ45/11 CONN LPC BUS P25 P33 MDC P29 P29 SATA HDD Connector P24 RTC CKT ENE KB926 LED P32 SATA ODD ConnectorP24 SPI P33 P21 ACCELEROMETER-1 P24 ST P30 P32 P33 Dock e-SATA Connector Int.KBD Touch Pad CONN USB2.0*1 ACCELEROMETER-2 P24 BOSCH RGB SPI ROM SST25VF080P31 RJ45 SPDIF P30 Audio board 、CIR Conn P29 MIC*1 K/B backlight Conn USB Board Conn USB conn x2 Capsense switch Conn LINE-OUT*1 P33 P33 Compal Secret Data Security Classification DC/DC Interface CKT P36 A 2006/02/13 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC P34 B C D Title Compal Electronics, Inc Block Diagram Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet E of 45 A Symbol Note : Voltage Rails O MEANS ON USB assignment: X MEANS OFF : means Digital Ground USB-0 Right side USB-1 Right side USB-2 Left side(with ESATA) : means Analog Ground USB-3 Dock power plane USB-4 Camera USB-5 WLAN +5VALW +B +1.8V +5VS +3VS +3VALW USB-7 Finger Printer 45@ : means need be mounted when 45 level assy or rework stage +1.5VS +0.9V USB-8 MiniCard(WWAN/TV) USB-9 Express card DEBUG@ : means just reserve for debug +VCCP State USB-6 Bluetooth @ : means just reserve , no build USB-10 X BATT @ : means need be mounted when 45 level assy or rework stage +CPU_CORE +2.5VS USB-11 X CONN@ : means ME part +1.8VS ESATA @ : means just reserve for ESATA PCIe assignment: PCIe-1 TV /WWAN/Robeson GS @ : means just reserve for G sensor S0 O O O O S1 O O O O S3 O O PCIe-3 WLAN PCIe-4 GLAN (Realtek) Multi @ : means just reserve for Multi Bay PCIe-5 Card reader NewC@ : means just reserve for New card X O PCIe-2 X FP @ : means just reserve for Finger Print PCIe-6 New Card DOCK@ : means just reserve for Docking S5 S4/AC O O X X Main@ : means just reserve for Main stream S5 S4/ Battery only O X X X OPP@ : means just reserve for OPP S5 S4/AC & Battery don't exist X X X X I2C / SMBUS ADDRESSING 2MiniC@ : means just reserve for 2nd Mini card slot PA @ : means just reserve for PA PR @ : means just reserve for PR DEVICE HEX ADDRESS DDR SO-DIMM A0 10100000 DDR SO-DIMM A4 10100100 CLOCK GENERATOR (EXT.) D2 11010010 SMBUS Control Table SOURCE SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMB_CK_CLK1 SMB_CK_DAT1 LCD_CLK LCD_DAT INVERTER BATT SERIAL EEPROM Thermal Sensor SODIMM CLK CHIP MINI CARD LCD Cap sensor board NEW CARD G sensor KB926 X V V X X X X X V X X KB926 X X X V X X X X X X X ICH9 X X X X V V V X X V V Cantiga X X X X X X X V X X X 43154432L01： ：Main@/DEBUG@/DOCK@/NewC@/FP@/ESATA@/GS@/Multi@/2MiniC@/PA@ ：Main@/DEBUG@/DOCK@/NewC@/FP@/ESATA@/GS@/PR@ 43154432L02： ：Main@/DEBUG@/DOCK@/NewC@/FP@/PR@ 43154432L03： 43154432L04： ：OPP@/DEBUG@/PR@ ：OPP@/DEBUG@/PR@ 43154432L05： PCB： ：DA600007110 ->M/B DAZ03V00200 ->Main DAZ03V00101 ->OPP Compal Secret Data Security Classification 2007/08/28 Issued Date 43154432L01： ： UMA GM PA FF (V) 43154432L02： ： UMA GM PR FF (V) 43154432L03： ： UMA GL PR FF43154432L04： ： UMA GM OPP (V) ： UMA GL OPP 43154432L05： ：SA00001P930 (SI-1、 、SI-2) Cantiga GM45 B0(QR32)： ICH9M A2 ES2 Base： ： SA00002AN10 (SI-1、 、SI-2) Cantiga GM45 B-2 QS QT62： ：SA00002JT10 (PV-1) ：SA00002JT50 (PV-2) Cantiga GM45 B-3 QS QU36： ICH9M A-3 QS - BASE QT09： ：SA00002JH00 (PV-1、 、PV-2) Cantiga GM45 B-3 QS SLB97： ：SA00002JJE0 (MV-1、 、MV-2) ：SA00002JHB0 (MV-1、 、MV-2) ICH9M A-3 QS -BASE SLB8Q： Deciphered Date 2006/03/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title Compal Electronics, Inc Notes List Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet of 45 60mA 50mA 25mA 1A D +V_BATTERY Dock 35mA 177mA INVPWR_B+ LVDS CON MDC 1.5 10mA ICH9 1A LAN 278mA 300mA AC VIN 1.7A 2A +3VALW 5.89A 3.39A 550mA B++ +3VS 1.5A JMB385 250mA 657mA C 0.3A 0.58A B+ +1.5VS +5VALW 2.2A 1.56A 1.3A ICH_VCC1_5 ICH9 1A ICH9 1A 35mA +5VS 10mA 7A 1.8A 700mA B 3.7A 3.7 X 3=11.1V DC BATT 1.9A B+++ 12.11A MCH A 1.8A DDR2 +1.8V 50mA 800Mhz 4G x2 1.05V_B+ 1.26A +VCCP 2.3A 2A A CPU_B+ 10mA +VCC_CORE +3VS_DVDD ALC268 34A/1.025V 50mA +3VALW_EC SPI ROM New card ICH9 +LCDVDD +3VS_CK505 C Mini card (WLAN) Mini card (TV tu/WWAN/Robeson) +VDDA IDT 9271B7 +5VAMP ODD SATA B Muti Bay PC Camera(4.75V) ICH9 MCH CPU CPU A Compal Secret Data Security Classification Issued Date 2007/08/28 Deciphered Date 2006/03/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Power delevry Size C Date: LVDS CON +0.9V 1.17A 4.7A Finger printer D 20mA 0.3A +3VAUX_BT Document Number Rev 1.0 Montevina Blade UMA LA4105P Saturday, July 18, 2009 Sheet of 45 A 1 Compal Secret Data Security Classification 2007/08/28 Issued Date Deciphered Date 2006/03/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title Compal Electronics, Inc Notes List Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet of 45 +3VS ITP-XDP Connector @R1 @ R1 XDP_DBRESET# H_A#[3 16] +VCCP R2 54.9_0402_1% XDP_TMS R3 54.9_0402_1% XDP_TDO R4 54.9_0402_1% XDP_TRST# R7 54.9_0402_1% XDP_TCK R8 54.9_0402_1% D JCPU1A H_ADSTB#1 H_STPCLK# H_INTR H_NMI H_SMI# A6 A5 C4 A20M# FERR# IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 D2 D22 D3 F6 LOCK# HIT# HITM# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# H_A20M# H_FERR# H_IGNNE# B IERR# INIT# RESET# RS[0]# RS[1]# RS[2]# TRDY# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# H_ADS# H_BNR# H_BPRI# H5 F21 E1 H_DEFER# H_DRDY# H_DBSY# F1 H_BR0# D20 B3 H_IERR# H_INIT# H4 H_LOCK# C1 F3 F4 G3 G2 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# G6 E4 H_HIT# H_HITM# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# THERMAL PROCHOT# THERMDA THERMDC ICH H_A20M# H_FERR# H_IGNNE# Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 BR0# ADDR GROUP_1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 C DEFER# DRDY# DBSY# H1 E2 G5 THERMTRIP# D21 A24 B25 C7 A22 A21 This shall place near CPU H_DEFER# H_DRDY# H_DBSY# H_BR0# T1 H_INIT# H_LOCK# Place TP with a GND 0.1" away H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# H_PROCHOT# H CLK BCLK[0] BCLK[1] H_ADS# H_BNR# H_BPRI# H_THERMDA_R H_THERMDC_R H_THERMTRIP# CLK_CPU_BCLK CLK_CPU_BCLK# 03/18 PV： ： Delete XDP connector C +3VS PV： ： Checklist Ver 1.5 change to 56 ohm 0.1U_0402_16V4Z K3 H2 K2 J3 L1 ADS# BNR# BPRI# CONTROL H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# XDP/ITP SIGNALS J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 XDP_DBRESET# R13 R14 R15 56_0402_1% 1 0_0402_5% 0_0402_5% +VCCP H_THERMDA H_THERMDC C3 H_THERMTRIP# +3VS CLK_CPU_BCLK CLK_CPU_BCLK# C2 U1 H_THERMDA H_THERMDC 2200P_0402_50V7K THERM# VDD R16 10K_0402_5% For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm SMCLK DP SMDATA DN ALERT# THERM# GND SMB_EC_CK2 SMB_EC_DA2 R6 SMB_EC_CK2 SMB_EC_DA2 10K_0402_5% +3VS 04/29 MV1 reserve 10K for 2nd source EMC1402-1-ACZL-TR_MSOP8 Address:100_1100 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil RESERVED H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17 35] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 ADDR GROUP_0 H_ADSTB#0 1K_0402_5% XDP_TDI D Change value in 5/02 PV： ： follow check list ver:1.5 change to 51 ohm 04/29 MV1 R2~R8 change to 54.9 Ohm, follow checklist 2.0 B PWM Fan Control circuit 04/29 MV1 change R14、 、 R15 to ohm +5VS 11/01 update Penryn JP2 +VCCP RB751V_SOD323 @ R17 56_0402_5% C4 4.7U_0805_10V4Z 2 D1 C5 0.1U_0402_16V4Z 2 GND GND ACES_88231-02001 CONN@ D Q2 E OCP# @ D2 G RLZ5.1B_LL34 FAN_PWM S SI3456BDV-T1-E3_TSOP6 Change PCB Footprint from ACES_85204-02001_2P to ACES_88231-02001_2P C OCP# @ Q1 MMBT3904_NL_SOT23-3 H_PROCHOT# B 2 +FAN +VCCP A A R18 56_0402_5% Compal Secret Data Security Classification H_IERR# 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Penryn(1/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet of 45 +VCC_CORE 1K_0402_5% 1K_0402_5% 1 T2 T3 T4 T5 T6 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 +V_CPU_GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] MISC DATA GRP D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# H_DSTBN#3 H_DSTBP#3 H_DINV#3 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# R23 R24 R25 R26 Penryn * Route the TEST3 and TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection B CPU_BSEL CPU_BSEL2 CPU_BSEL1 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal COMP[0,2] trace width is 18 mils COMP[1,3] trace width is mils CPU_BSEL0 166 1 200 266 0 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] D +VCCP R19 G21 +VCCPA +VCCPB V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] 1 2 0_0402_5% 0_0402_5% C R20 + C6 330U_D2E_2.5VM_R7 B26 C26 VCCA[01] VCCA[02] +1.5VS AD6 AF5 AE5 AF4 AE3 AF3 AE2 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 AF7 VCCSENSE AE7 VSSSENSE C7 0.01U_0402_16V7K @ R21 @ R22 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#[48 63] 27.4_0402_1% H_DSTBN#1 H_DSTBP#1 H_DINV#1 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 DATA GRP C H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 JCPU1C 54.9_0402_1% H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16 31] D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 27.4_0402_1% D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DATA GRP D E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 +VCC_CORE H_D#[32 47] JCPU1B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 54.9_0402_1% H_D#[0 15] DATA GRP 10U_0805_6.3V6M VCCSENSE C8 Near pin B26 VSSSENSE B Penryn Length match within 25 mils The trace width/space/other is 20/7/25 +VCCP +VCC_CORE R27 1K_0402_1% +V_CPU_GTLREF R28 100_0402_1% VCCSENSE R30 100_0402_1% VSSSENSE R29 2K_0402_1% Close to CPU pin within 500mils Close to CPU pin AD26 within 500mils A Compal Secret Data Security Classification 2007/08/28 Issued Date A 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Penryn(2/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet of 45 +VCC_CORE Place these capacitors on L8 (North side,Secondary Layer) C9 10U_0805_6.3V6M C10 10U_0805_6.3V6M C11 10U_0805_6.3V6M C12 10U_0805_6.3V6M C13 10U_0805_6.3V6M C14 10U_0805_6.3V6M C15 10U_0805_6.3V6M C16 10U_0805_6.3V6M D D +VCC_CORE JCPU1D B P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 Place these capacitors on L8 (North side,Secondary Layer) C17 10U_0805_6.3V6M C18 10U_0805_6.3V6M C19 10U_0805_6.3V6M C20 10U_0805_6.3V6M C21 10U_0805_6.3V6M C22 10U_0805_6.3V6M C23 10U_0805_6.3V6M C24 10U_0805_6.3V6M +VCC_CORE Place these capacitors on L8 (North side,Secondary Layer) C25 10U_0805_6.3V6M C26 10U_0805_6.3V6M C27 10U_0805_6.3V6M C28 10U_0805_6.3V6M C29 10U_0805_6.3V6M C30 10U_0805_6.3V6M C31 10U_0805_6.3V6M C32 10U_0805_6.3V6M +VCC_CORE Place these capacitors on L8 (North side,Secondary Layer) C33 10U_0805_6.3V6M C34 10U_0805_6.3V6M C35 10U_0805_6.3V6M C36 10U_0805_6.3V6M C37 10U_0805_6.3V6M C38 10U_0805_6.3V6M C39 10U_0805_6.3V6M C40 10U_0805_6.3V6M C Mid Frequence Decoupling ESR 1980uF Near CPU CORE regulator C41 + @ C42 + + C43 + C44 330U_D2_2VY_R7M +VCC_CORE 330U_D2_2VY_R7M VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] 330U_D2_2VY_R7M VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] 330U_D2_2VY_R7M C A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 B 11/21 Change ESR=7m ohm +VCCP C45 0.1U_0402_10V6K Inside CPU center cavity in rows C46 0.1U_0402_10V6K C47 0.1U_0402_10V6K C48 0.1U_0402_10V6K C49 0.1U_0402_10V6K C50 0.1U_0402_10V6K Penryn A A Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Penryn(3/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet of 45 B +H_VREF A11 B11 AY21 T25 T26 T27 T28 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 R38 10K_0402_5% R39 10K_0402_5% R40 10K_0402_5% CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 0.1U_0402_16V4Z Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20 PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK THERMTRIP# DPRSLPVR @ C55 2 R54 R55 1 C59 R48 10K_0402_1% C57 2 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 BC28 AY28 AY36 BB36 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 BA17 AY16 AV16 AR13 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 BD17 AY17 BF15 AY13 M_ODT0 M_ODT1 M_ODT2 M_ODT3 SM_RCOMP SM_RCOMP# BG22 BH21 SMRCOMP SMRCOMP# BF28 BH28 SMRCOMP_VOH SMRCOMP_VOL AV42 AR36 BF17 BC36 V_DDR_MCH_REF SM_PWROK SM_REXT TP_SM_DRAMRST# B38 A38 E41 F41 CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# F43 E43 CLK_MCH_3GPLL CLK_MCH_3GPLL# AE41 AE37 AE47 AH39 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AE40 AE38 AE48 AH40 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AE35 AE43 AE46 AH42 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AD35 AE44 AF46 AH43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# PEG_CLK PEG_CLK# R29 B7 N33 P32 AT40 AT11 T20 R32 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 R34 R35 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_ODT0 M_ODT1 M_ODT2 M_ODT3 D +1.5V 80.6_0402_1% 80.6_0402_1% 1 Follow Design Guide For Cantiga: 80.6ohm @ R36 R37 0_0402_5% 499_0402_1% 1 SM_DRAMRST# CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL# C DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 GFX_VR_EN B33 B32 G33 F33 E33 T30 T31 T32 T33 T34 C34 T35 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AH37 AH36 AN36 AJ35 AH34 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 R1120 10K_0402_5%~D D25 +1.5V SYSON CH751H-40PT_SOD323-2 SM_PWROK DDR3_SM_PWROK B +VCCP CL_CLK0 CL_DATA0 M_PWROK CL_RST# +CL_VREF TSATN# HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC N28 M28 G36 E36 K36 H36 B12 HDMICLK_NB HDMIDAT_NB CLKREQ#_7 MCH_ICH_SYNC# TSATN# R737 B28 B30 B29 HDA_SDIN2_NB C29 A28 R43 1K_0402_1% CL_CLK0 CL_DATA0 M_PWROK CL_RST# 0621 add CLK and DAT for DVI DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# T36 T37 C56 0.1U_0402_16V4Z R44 499_0402_1% HDMICLK_NB HDMIDAT_NB CLKREQ#_7 MCH_ICH_SYNC# 56_0402_5% +VCCP TSATN# *R44*Follow Intel feedback HDA_BITCLK_NB R210 HDA_RST#_NB HDA_SDIN2 A HDA_SDOUT_NB 33_0402_5% HDA_SYNC_NB 0830 Add pull-up and pull-down resistor 2007/08/28 Issued Date Near B3 pin Compal Secret Data Security Classification 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 CANTIGA ES_FCBGA1329 PV： ： follow check list ver:1.5 change to 10K ohm within 100 mils from NB 1 221_0603_1% 0.1U_0402_16V4Z C58 +H_SWNG 0.1U_0402_16V4Z 100_0402_1% 0.1U_0402_16V4Z 2K_0402_1% R52 H_RCOMP 24.9_0402_1% 1K_0402_1% +H_VREF A R45 10K_0402_1% V_DDR_MCH_REF M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 NC +V_DDR_MCH_REF generated by DC-DC R47 AR24 AR21 AU24 AV20 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK R41 100_0402_5% R42 0_0402_5% +VCCP SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# MCH_CLKSEL0 T25 MCH_CLKSEL1 R25 MCH_CLKSEL2 P25 P20 P24 CFG5 C25 CFG6 N24 CFG7 M24 CFG8 E21 CFG9 C23 CFG10 C24 CFG11 N21 CFG12 P21 CFG13 T21 CFG14 R20 CFG15 M20 CFG16 L21 CFG17 H21 CFG18 P29 CFG19 R28 CFG20 T28 +1.5V R46 RESERVED RESERVED RESERVED RESERVED M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 PLT_RST# H_THERMTRIP# DPRSLPVR +VCCP BG23 BF23 BH18 BF18 RESERVED CLK H_ADS# H_ADSTB#0 PM_EXTTS#1 H_ADSTB#1 H_BNR# H_BPRI# CLKREQ#_7 H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# CANTIGA ES_FCBGA1329 Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces T24 DDR CLK/ CONTROL/COMPENSATION 0.01U_0402_25V7K R33 1K_0402_1% PM_EXTTS#0 Layout note: RESERVED RESERVED RESERVED +3VS H_AVREF H_DVREF Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 H_RS#0 H_RS#1 H_RS#2 B31 B2 M1 B6 F12 C8 2 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 SMRCOMP_VOL 0.01U_0402_25V7K B15 K13 F13 B13 B14 C52 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 2.2U_0603_6.3V4Z C51 L9 M8 AA6 AE5 20% of 1.5V VCC_SM T21 T22 T23 AP24 AT21 AV24 AU20 H_RS#_0 H_RS#_1 H_RS#_2 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 R32 3.01K_0402_1% SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 H_CPURST# H_CPUSLP# L10 M7 AA5 AE6 R31 1K_0402_1% RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 SMRCOMP_VOH 80% of 1.5V VCC_SM 1 H_SWING H_RCOMP J8 L3 Y13 Y1 M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 DMI H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 GRAPHICS VID C12 E11 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 +1.5V ME H_RESET# H_CPUSLP# H_RESET# H_CPUSLP# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 MISC C5 E3 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 CFG +H_SWNG H_RCOMP H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 RSVD C U2B C54 D F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 2.2U_0603_6.3V4Z C53 H_D#[0 63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_A#[3 35] HOST U2A HDA Title Compal Electronics, Inc Cantiga(1/6)-AGTL/DMI/DDR Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet of 45 D D DDR_B_D[0 63] B BB20 BD20 AY20 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# MEMORY A DDR_A_DM[0 7] SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 DDR_A_DQS[0 7] DDR_A_DQS#[0 7] DDR_A_MA[0 14] CANTIGA ES_FCBGA1329 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 BC16 BB17 BB33 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 SB_RAS# SB_CAS# SB_WE# AU17 BG16 BF14 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 B SA_RAS# SA_CAS# SA_WE# BD21 BG18 AT25 U2E DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 MEMORY SA_BS_0 SA_BS_1 SA_BS_2 SYSTEM SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 DDR C AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 SYSTEM U2D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 DDR DDR_A_D[0 63] SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# DDR_B_DM[0 7] DDR_B_DQS[0 7] DDR_B_DQS#[0 7] DDR_B_MA[0 14] C B CANTIGA ES_FCBGA1329 A A Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Cantiga(2/6)-DDR2 A/B CH Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet 10 of 45 SPI ROM D D +3VL U27 20mils C712 0.1U_0402_16V4Z FSEL# SPI_CLK FWR# SPI_FSEL# 10_0402_5% SPI_CLK_R 10_0402_5% SPI_FWR# 10_0402_5% R553 R554 R556 VSS W VCC HOLD S C D Q SPI_SO R555 FRD# 0_0402_5% FRD# WIESON G6179 8P SPI C307 C308 33_0402_5% 22P_0402_50V8J 33_0402_5% R232 SPI_FWR# C 22P_0402_50V8J 33_0402_5% C309 +3VL +3VL 1 R231 SPI_CLK_R SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH WIESO_G6179-100000_8P @ 22P_0402_50V8J C711 0.1U_0402_16V4Z 12/27EMI request C R552 @ 100K_0402_5% U28 @ SMB_EC_CK1 SMB_EC_DA1 Remove LPC Debug Port 20090618 R230 SPI_FSEL# VCC WP SCL SDA A0 A1 A2 GND 11/16 Change TO +3VALW 02/18 Change TO +3VL 02/18 Delete KBC EEPROM AT24C16AN-10SI-2.7_SO8 R557 @ 100K_0402_5% HDCP ROM +3VS +3VS @ R411 @ R412 +3VS SPI_WP# 3.3K_0402_5% SPI_HOLD# 3.3K_0402_5% @ C304 0.1U_0402_16V4Z U6 @ @ R413 1K_0402_5% SPI_SB_CS# SPI_CLK_SB SPI_SI @ R414 SPI_SB_CS# B 2 B SPI_WP# SPI_HOLD# SPI_CLK_SB 15_0402_5% SPI_SI VCC VSS W HOLD S C D Q @ R415 SPI_SO_L SST25LF080A_SO8-200mil SPI_SO_R SPI_SO_R 15_0402_5% 11/17 Add SB HDCP ROM Change HDCP ROM to +3VS 01/03 02/13 Sparate SPI_CLK between SB and EC A A Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/07/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc BIOS ROM Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Saturday, July 18, 2009 Sheet 31 of 45 +3VL_EC C301 +1.5VS BATT_OVP 33_0402_5% 15P_0402_50V8J CLK_PCI_EC 47K_0402_5% R578 +3VL 0.1U_0402_16V4Z 2 C721 EC_SCI# J1 PCI_RST# HDA_RST#_EC R403 11/09 Delete CLKRUN# 11/09 Add HDA_RST# to EC JOPEN PCI_RST# 1 R713 100K_0402_5% R581 8.2K_0402_5% @R124 @ R124 10K_0402_5% R583 10K_0402_5% R721 10K_0402_5% 2 2 R213 8.2K_0402_5% +3VS SUSP# SYSON +3VL +3VL LID_SW# TP_BTN# 01/03 Change to +3VS 11/07 Add SYSON and SUSP# PD @ R585 10K_0402_5% PCI_PME# 0_0402_5% 11/15 Delete PCI_PME# @ R589 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 R191 10K_0402_5% SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 77 78 79 80 EC_PME# SLP_S3# SLP_S5# EC_SMI# LID_SW# OUT IN PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 BATT_TEMP BATT_OVP ADP_I ADP_ID TP_BTN# ANA_MIC_DET 68 70 71 72 DAC_BRIG VCTRL IREF AC_SET 83 84 85 86 87 88 EC_MUTE# USB_EN# I2C_INT MUTE_LED TP_CLK TP_DATA 97 98 99 109 R582 DOCK_VOL_UP# DOCK_VOL_DWN# 119 120 126 128 R227 R228 R229 73 74 89 90 91 92 93 95 121 127 C726 KSO14 @C795 @ C795 100P_0402_50V8J KSO13 @C796 @ C796 100P_0402_50V8J KSO12 @C797 @ C797 100P_0402_50V8J BATT_TEMP BATT_OVP ADP_I ADP_ID TP_BTN# ANA_MIC_DET KSO3 @C798 @ C798 100P_0402_50V8J KSO6 @C799 @ C799 100P_0402_50V8J KSO8 @C800 @ C800 100P_0402_50V8J KSO7 @C801 @ C801 100P_0402_50V8J KSO4 @C802 @ C802 100P_0402_50V8J KSO2 @C803 @ C803 100P_0402_50V8J KSI0 @C804 @ C804 100P_0402_50V8J KSO1 @C805 @ C805 100P_0402_50V8J KSO5 @C806 @ C806 100P_0402_50V8J KSI3 @C807 @ C807 100P_0402_50V8J KSI2 @C808 @ C808 100P_0402_50V8J KSO0 @C809 @ C809 100P_0402_50V8J KSI5 @C810 @ C810 100P_0402_50V8J KSI4 @C811 @ C811 100P_0402_50V8J KSO9 @C812 @ C812 100P_0402_50V8J KSI6 @C813 @ C813 100P_0402_50V8J KSI7 @C814 @ C814 100P_0402_50V8J KSI1 @C815 @ C815 100P_0402_50V8J DAC_BRIG VCTRL IREF AC_SET EC_MUTE# USB_EN# I2C_INT MUTE_LED R579 R580 0.1U_0402_16V4Z L31 10K_0402_5% 10K_0402_5% TP_CLK TP_DATA 02/13 Correct AC_LED control by EC 0_0402_5% AC_LED# DOCK_VOL_UP# DOCK_VOL_DWN# 1 2 11/09 don't stuff when use C0 FRD# FWR# SPI_CLK FSEL# 33_0402_5% 47_0402_5% 33_0402_5% 10K_0402_5% CIR_IN CIR_IN FSTCHG STD_ADP CAPS_LED# BAT_LED# ON/OFFBTN_LED# VR_ON R586 EC_RSMRST# 100 101 R588 EC_ON 0_0402_5% 102 WL_BLUE_LED# 103 PM_PWROK_R 104 105 M_PWROK 106 TP_LED# 107 108 FRD# FWR# SPI_CLK FSEL# 11/09 PU +5VL move to M/B SPI_CLK 10K_0402_5% R1132 10K_0402_5% EC_RSMRST# EC_LID_OUT# EC_ON WL_BLUE_LED# R254 100_0402_5% 2 22_0402_5% R1131 M_PWROK TP_LED# +5VL FSTCHG STD_ADP CAPS_LED# BAT_LED# ON/OFFBTN_LED# VR_ON AC_IN C818 22P_0402_50V8J DOCK_VOL_UP# SYSON SLP_S4# ENBKL EAPD_CODEC THERM_SCI# SUSP# PWRBTN_OUT# NMI_DBG# PM_PWROK BKOFF# PV PWROK sequence issue 11/07 Add SLP_S4# SLP_S4# ENBKL EAPD_CODEC THERM_SCI# SUSP# PWRBTN_OUT# +3VL 124 C724 4.7U_0603_6.3V6K NMI_DBG# AC_IN JP19 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1 +3VL D16 CH751H-40PT_SOD323-2 R714 10K_0402_5% D14 +3VL 0_0603_5% 14" INT_KBD CONN.( TYPE "D" KB) to South bridge ADP_ID PCI_SERR# PCI_SERR# CH751H-40PT_SOD323-2 11/07 Correct direction pretect leakage R715 150K_0402_5% D13 04/29 MV1 Change to 150K ACIN ACIN +3VS R407 10K_0402_5% DOCK_VOL_DWN# R408 10K_0402_5% Current limit 110 112 114 115 116 117 118 For C Revision L30 0_0603_5% LAN_POWER_OFF_R 63 64 65 66 75 76 KB926QFB0_LQFP128_14X14 0_0805_5% 2 GPI +EC_AVCC EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 +3VL_EC R443 CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 CRY1 2 100P_0402_50V8J INV_PWM FAN_PWM EC_BEEP ACOFF 0.01U_0402_16V7K ECAGND C720 2 22_0402_5% R720 V18R C725 15P_0402_50V8J 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ACES_85201-2405 CONN@ CH751H-40PT_SOD323-2 0_0402_5% +3VL R1099 4.7K_0402_5% R1100 4.7K_0402_5% ESB_CLK ESB_DAT C791 R731 R732 1 C315 @ 10P_0402_25V8K 2 33_0402_5% ESB_CLK_R 33_0402_5% ESB_DAT_R 02/20 PV EMI reserve C315 near EC 100P_0402_50V8J Vendor Recommend +3VL LAN_POWER_OFF SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# XCLK1 XCLK0 NC EC DEBUG UTXport @ R233 SPI Flash ROM PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A 32.768KHZ_12.5P_1TJS125DJ2A073 R1130 FAN_PWM EC_BEEP ACOFF SPI Device Interface SM Bus @ R595 20M_0402_5% PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 11 24 35 94 113 NC 03/13 PV2 Add EMI solution PS2 Interface GPIO SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 21 23 26 27 +5V_TP GND GND GND GND GND Y5 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F DA Output KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 0_0402_5% AD PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 EC_PME# SLP_S3# SLP_S5# 14 EC_SMI# 15 LID_SW# 16 ESB_CLK_R 17 ON/OFFBTN ESB_DAT_R R592 18 DOCK_SLP_BTN# EC_PME# 0_0402_5% 19 @ R591 0_0603_5% 25 11/07 Connect DOCK_SLP_BTN# to TSATN# CONA# 28 CONA# ON/OFFBTN WWAN_POWER_OFF 29 WWAN_POWER_OFF UTX 30 UTX LAN_POWER_OFF_R R5931 31 +3VL ON/OFFBTN 4.7K_0402_5% 32 ON/OFFBTN EC_PME# PCI_RST# DIM_LED 34 DIM_LED NUM_LED# 36 NUM_LED# 1 C723 C324 C325 15P_0402_50V8J CRY2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 122 2 123 R190 OPP@ WL_BLUE_BTN PWM Output +3VALW +3VL 12 13 37 20 0_0402_5% 38 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 11/17 Change to +3VALW 04/29 MV1 Change to +3VALW CLK_PCI_EC PCI_RST# ECRST# INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 MISC @C794 @ C794 C1408 100P_0402_50V8J KSO11 02/13 Add HDA level shift 4.7U_0603_6.3V6K @C793 @ C793 R1133 100K_0402_5% @ R576 GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & @ C722 1 10 100P_0402_50V8J KSO10 Q21 MMBT3904_NL_SOT23-3 Current limit GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 03/28 PV2 Change SM bus power to +3VL GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 @C792 @ C792 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% KSO15 2 2 VCC VCC VCC VCC VCC VCC 1 1 HDA_RST#_EC C R573 R577 R574 R575 HDA_RST#_CODEC 11/09 EC recommend R251 10K_0402_5% For EMI E +3VS U30 SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2 R250 56_0402_5% 0_0805_5% B 04/22 MV1 Change SMbus1 power to +3VL +3VL +EC_AVCC +3VL_EC R572 1 100P_0402_50V8J +3VL C719 67 C718 AVCC C717 2 1000P_0402_50V7K AGND C716 69 C715 2 0.1U_0402_16V4Z +3VS 1000P_0402_50V7K ECAGND 0.1U_0402_16V4Z 22 33 96 111 125 0.1U_0402_16V4Z 1 Compal Secret Data Security Classification Issued Date 2007/08/28 Deciphered Date 2006/07/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc EC KB926/KB Conn Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Saturday, July 18, 2009 Sheet 32 of 45 B HDD LED +3VS +5VS D12 PA@ AMBER R718 10K_0402_5% D17 ON/OFFBTN_LED# White R980 HT-F196BP5_WHITE System Power LED +5VALW_LED 200_0402_5% 1 PR 11/07 Change part number White 02/13 Add PR TP LED QSMF-C16E_AMBER-WHITE TP_LED# #PV reserve LDO for capacitor sensor board 03/28 PV2 Delete LDO AMBER White D21 PR@ TP_BTN# PA @ C317 0.33U_0603_10V7K Amber QSMF-C16E_AMBER-WHITE VOUT White R728 200_0402_5% VIN APL5151-33BC-TRL SOT23 5P 3.3V @ C316 1U_0603_10V4Z Amber GND 1 White +5VS_LED BP 10K_0603_1% SHDN# Amber AMBER @ U7 R609 200_0402_5% R253 R610 200_0402_5% R611 @ 10K_0402_5% SW1 TJG-533-V-T/R_6P 3 +3VL_CAP @ R1098 200_0402_5% GS@ HDDHALT_LED# +5VL 200_0402_5% +5V_TP +5VS_LED +3VL_CAP +5VALW_LED PJP703 PAD-OPEN 2x2m White SATA_LED# Battery Charge LED 2 HT-F196BP5_WHITE D53 White +3VL R1097 BAT_LED# TP ON/OFF TouchPAD ON/OFF LED 470_0402_5% White D52 Cap lock +5VS_LED QSMF-C16E_AMBER-WHITE 2 G Q4 2N7002_SOT23-3 HT-F196BP5_WHITE E T/P Board (Inculde T/P_ON/OFF) R1095 1 D White D50 CAPS_LED# D System LED C A S TP_LED# On (TP_LED#=L)-> White Off (TP_LED#=H)-> Amber 02/22 Add C on +3VL @ C310 33_0402_5% C323 15P_0402_50V8J 1 2 15P_0402_50V8J 01/03 EMI request 4.7U_0603_6.3V6K 2 ACES_85201-1005N CONN@ C313 02/25 EMI request 2 G1 G2 TP_CLK TP_DATA TP_CLK TP_DATA ACES_85201-04051 CONN@ D SYSON G SYSON JP23 C729 0.1U_0402_16V4Z @ Q24 2N7002_SOT23-3 02/25 EMI request Add D28 and C729 @ C730 100P_0402_50V8J S 1 2 @C731 @ C731 100P_0402_50V8J 03/13 PV2 Add EMI solution Mini card LED Keyboard backlight Conn +3VS R193 10K_0402_5% ON/OFF Button Connector Q23 @ SI2301BDS-T1-E3_SOT23-3 I2C_INT EMI request 1 NUM_LED# @ R234 +5V_TP @ R612 10K_0402_5% 1 ESB_CLK 0_0603_5% 3 0_0402_5% 0_0402_5% 33_0402_5% 33_0402_5% 0_0402_5% 0_0402_5% 1 Cypress 2 2 10 GND GND D R730 R238 1 1 R691 JP59 10 11 12 G Main@ SMB_EC_DA1 OPP@ NUM_LED# SMB_EC_DA1 ON/OFFBTN R237 R729 R56 R149 +5V_TP S OPP@ SMB_EC_CK1 Main@ ESB_CLK Main@ ESB_DAT Main@ ON/OFFBTN_LED# SMB_EC_CK1 ESB_CLK ENE ESB_DAT I2C_INT +5VALW 2 0_0402_5% 0_0402_5% 1 D28 PSOT24C_SOT23-3 + C322 @ 22U_A_4VM C326 0.1U_0402_16V4Z R151 R169 R53 0_0805_5% OPP@ C329 15P_0402_50V8J OPP@ OPP@ WL_BLUE_LED# R51 0_0805_5% Main@ TP_DATA TP_CLK T/P Board Conn 1 +3VL WL_BLUE_BTN 04/29 MV1 Delete C322 +5VALW_LED Capacitor 02/13 Add ON/OFFBTN_LED# and ON/OFFBTN Sensor Conn on Cap board connector for OPP +5VS_LED +3VL_CAP +5VALW_LED @ R205 JP9 2 0_0805_5% G1 G2 WL_BLUE_LED# G1 G2 Q11 2N7002_SOT23-3 ACES_85201-04051 CONN@ ACES_85201-04051 CONN@ BT_LED +5VS_LED 1 D JP10 ON/OFFBTN ON/OFFBTN_LED# S G R716 100K_0402_5% 01/03 Keyboard backlight reserve a 0805 size resistor C246 0.1U_0402_16V4Z @ R252 @R252 C260 D24 WW_LED# 33_0402_5% CH751H-40PT_SOD323-2 R257 2 0_0402_5% WL_LED CH751H-40PT_SOD323-2 15P_0402_50V8J JP11 4 02/20 PV change to doide G1 G2 ACES_85201-04051 CONN@ 02/20 EMI 01/03 Change Lid switch connector type request 02/18 Support Hall sensor module, move C243、 、 C246 to M/B 03/18 Delete Lid switch pin 04/29 MV1 Change LID switch power to +3VL A WL_LED# D58 +3VL LID_SW# C243 10P_0402_25V8K ESB_DAT @ Lid Switch Connector B 11/20 Reserve WW_LED function Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/07/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C D Title Compal Electronics, Inc KBD, ON/OFF, SW, CIR Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Saturday, July 18, 2009 Sheet E 33 of 45 Atlas/ Saturn Dock JDOCK1 DOCK_PWR_ON Spec 0V = Notebook S4/S5, Dock off 2.5V = Notebook S3, Dock on DOCK@ 4V = Notebook on R974 S0, Dock 1K_0402_5% +5VS R975 1 DOCK_PWRON DAN202U_SC70 DOCK@ RJ45_MIDI1RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+ RJ45_MIDI1RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+ D S +V_BATTERY G Q58 2N7002_SOT23-3 DOCK@ R976 10K_0402_5% DOCK@ CRT_Red CRT_Green CRT_Blue DDC_DATA DDC_Clock Hsync Vsync USBUSB+ Digital gnd MDI3MDI3+ MD2IMDI2+ MDI1MDI1+ MDI0MDI0+ Battery out Battery out Digital gnd TV Luma TV chroma TV composite TV ground CIR input PWR_ON Mute_LED Sleep Botton Jack Detect VOL_up VOL_down SPDIF Audio Output gnd Right headphone Left headphone Mic_Right Mic_Left Mic gnd Dock_present PJP3 B+ GND GND GND GND 45 46 PAD-OPEN 2x2m GND GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 12/18 Correct GND Delete TVout function from 11/07 +DOCKVIN C306 @ 1000P_0402_50V7K C734 1000P_0402_50V7K DOCK@ GNDA 11/17 Reserve D G R623 2K_0402_5% DOCK@ S Q27 2N7002_SOT23-3 DOCK@ L36 DOCK@ FBM-11-160808-601-T_0603 DOCK_MIC_R_C DOCK_MIC_R C744 DOCK@ DOCK_MIC_L_C L37 DOCK@ FBM-11-160808-601-T_0603 DOCK_MIC_L C754 220P_0402_50V7K DOCK@ 1 C755 220P_0402_50V7K DOCK@ C740 DOCK@ C745 DOCK@ DOCK_LOUT_R DOCK_LOUT_L GNDA C741 DOCK@ GNDA S R722 @ 33_0402_5% Q29 2N7002_SOT23-3 DOCK@ 1 G B @ Q55 2N7002_SOT23-3 Q30 MMBT3904_NL_SOT23-3 DOCK@ G SPDIFO_L R977 DOCK@ 220_0402_5% SPDIF_OUT 0.1U_0402_16V7K R723 DOCK@ 0_0603_5% S C757 R633 47K_0402_5% DOCK@ C64 DOCK@ D E C819 220P_0402_25V8J DOCK@ Q32 MMBT3904_NL_SOT23-3 C DOCK@ B E +1.5VS_HDA D 1 C DOCK_MIC_L_C 2 SENSE_B# R625 10K_0402_5% DOCK@ R626 10K_0402_5% DOCK@ R632 10K_0402_5% DOCK@ 11/17 Recommend GNDA GNDA +3VS 22_0402_5% DOCK@ 0.01U_0402_16V7K R_VOL_UP# R_VOL_DWN# Need 600 Ohm 500 mA 0.01U_0402_16V7K MIC_Dock CONA# 1000P_0402_50V7K R621 10K_0402_5% 2 1000P_0402_50V7K +3VL R979 DOCK_PRESENT C305 @ 11/12 Change to +3VL Dock PRESENT MUTE_LED DOCK_SLP_BTN# JACK_DET# DOCK_VOL_UP# DOCK_VOL_DWN# +DOCKVIN 41 42 43 44 CONN@ FOX_QL1122L-H212AR-7F 02/13 Add 33 ohm for isolate Docking VGA_GND CIR_IN CIR_IN DOCK_PWRON D_MUTE_LED R246 33_0402_5% D_DOCK_SLP_BTN# R247 33_0402_5% JACK_DET# R_VOL_UP# R617 200_0402_5% R_VOL_DWN# R618 200_0402_5% SPDIFO_L DOCK@ AUDIO_OGND GNDA DOCK@ DOCK_LOUT_R DOCK_LOUT_R DOCK_LOUT_L DOCK_LOUT_L DOCK_MIC_R_C DOCK_MIC_L_C AUDIO_IGND GNDA DOCK_PRESENT R620 2K_0402_5% 1000P_0402_50V7K SYSON# 38 40 34 36 30 32 26 28 22 24 18 20 14 16 10 12 12/18 Correct GND D57 DOCK@ 1K_0402_5% +3VALW RED GREEN BLUE D_DDCDATA D_DDCCLK D_HSYNC D_VSYNC USB20_N3 USB20_P3 RED GREEN BLUE D_DDCDATA D_DDCCLK D_HSYNC D_VSYNC USB20_N3 USB20_P3 R978 110_0402_5% DOCK@ 1U_0603_10V6K DOCK@ Compal Secret Data Security Classification Issued Date 2007/08/28 Deciphered Date 2006/03/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc DOCK CONN Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet 34 of 45 VCC3V 1 2 D PV 02/20 follow datasheet 36 35 11/07 Enable DDC_EN pin 34 33 R651 0_0402_5% @ R652 0_0402_5% @ R654 0_0402_5% R655 0_0402_5% +3VS_LS 32 +3VS_LS 31 30 HDMI_DETECT 29 HDMIDAT 28 HDMICLK 27 26 +3VS_LS +3VS_LS GND 25 CH7318A-BF-TR_QFN48_7X7 TMDS_B_HPD# G @C769 HDMICLK+ R744 7.5K_0402_1% S 2N7002_SOT23-3 @ R656 HDMICLK- 68_0402_5% +3VS_LS 0.5P_0402_50V8B @R657 @ R657 68_0402_5% +3VS_LS @C770 @ C770 HDMI_TX_0+ 0.5P_0402_50V8B HDMI_TX_1- @ R743 20K_0402_5% HDMI_TX_0@ Q28 TMDS_B_HPD C 24 OUT_D1- OE* 23 13 OUT_D1+ GND TMDS_B_HPD# +3VS_LS 37 38 39 40 GND VCC3V C D 0_0603_5% GND IN_D1- IN_D1+ 42 43 44 45 46 41 VCC3V IN_D2- IN_D2+ GND IN_D3- IN_D3+ ANALOG2 0_0402_5% @ R742 20K_0402_5% 47 SCL_SINK 22 TMDS_B_HPD# SCL_SOURCE SDA_SINK VCC3V TMDS_B_HPD 12 SDA_SOURCE 21 11 +3VS_LS R9 +3VS_LS HPD_SINK OUT_D2- 10 GND HPD_SOURCE 20 HDMICLK_NB ANALOG1(REXT) OUT_D2+ HDMIDAT_NB DDC_EN 19 GND GND VCC3V 18 475_0402_1% TMDS_B_HPD FUNCTION3 PC1 OUT_D3- R653 PC0 FUCNTION2 17 2 R650 2.2K_0402_5% FUNCTION1 OUT_D3+ 16 4.7K_0402_5% FUNCTION4 VCC3V 4.7K_0402_5% GND VCC3V 15 R255 @R256 @ R256 GND OUT_D4- OUT_D4+ +3VS_LS 14 1 +3VS_LS VCC3V 48 IN_D4+ PV 02/20 follow datasheet R649 2.2K_0402_5% IN_D4- U43 Follow Intel Feedback putting 2.2K ohm R648 +3VS 10U_0805_6.3V6M TMDS_B_DATA0 TMDS_B_DATA0# 0.1U_0402_10V6K C318 TMDS_B_DATA1 TMDS_B_DATA1# TMDS_B_CLK# TMDS_B_CLK D +3VS_LS +3VS_LS TMDS_B_DATA2# TMDS_B_DATA2 C321 EQUALIZATION SETTING: [PC1,PC0]=00,8dB [PC1,PC0]=01,4dB (Recommanded) [PC1,PC0]=10,12dB [PC1,PC0]=11,0dB 0.1U_0402_10V6K C319 +3VS_LS 0.01U_0402_16V7K C320 @C771 HDMI_TX_2+ HDMI_TX_2- Follow Vendor Feedback 11/07 correct TMDS_B_HPD# connection to North bridge R1121 @ R658 @ @R659 @ R659 68_0402_5% 68_0402_5% 0.5P_0402_50V8B @C772 @ C772 HDMI_TX_1+ 0.5P_0402_50V8B 02/20 PV EMI request add C273、 、 C314 HDMI Connector 0_0402_5% +5VS @ L38 R1123 WCM-2012-670T_0805 HDMI_CLK+ 0_0402_5% 0_0402_5% PU 11/07 Follow recommend change to 3.9K HDMI_TX_0+ 4 R49 3.9K_0402_1% 1 2200P_0402_25V7K B +5VS_HDMI L39 HDMI_TX_0- C273 RB411D T146 _SOT23-3 D31 Vendor suggests 4K 1 R1122 HDMI_CLK- HDMI_TX0- WCM-2012-670T_0805 HDMI_TX0+ R1124 0_0402_5% R1125 0_0402_5% HDMICLK+ B 2 R50 3.9K_0402_1% HDMICLK- 0.1U_0402_16V4Z C773 C314 @ 2200P_0402_25V7K JHDMI1 L41 HDMI_DETECT WCM-2012-670T_0805 HDMI_TX1+ HDMI_TX1- D32 SKS10-04AT_TSMA R1126 0_0402_5% R1127 0_0402_5% R665 1K_0402_1% L40 R666 10K_0402_1% 18 16 15 19 HDMI_CLKHDMI_CLK+ HDMI_TX0HDMI_TX0+ HDMI_TX1HDMI_TX1+ HDMI_TX2HDMI_TX2+ 12 10 FBML10160808121LMT_0603 C774 330P_0402_50V7K 2 HDMI_TX_1+ 1 HDMI_TX_1- HDMIDAT HDMICLK +5V SDA SCL HP_DET CKCK+ D0D0+ D1D1+ D2D2+ L42 HDMI_TX_2A HDMI_TX_2+ R1128 2 13 14 GND GND GND GND GND GND GND GND DDC/CEC_GND 11 20 21 22 23 17 HDMI_TX2SUYIN_100042MR019S153ZL CONN@ WCM-2012-670T_0805 HDMI_TX2+ A 0_0402_5% Compal Secret Data Security Classification 01/03 Reserver ohm co lay with common choke 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC CEC Reserved Title Compal Electronics, Inc HDMI LS & Conn Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet 35 of 45 +5VALW to +5VS Transfer +5VALW B+ +3VALW +3VS RUNON_3VS D 1 DIM_LED 2 0.01U_0402_16V7K +5VS D S 2N7002DW-7-F_SOT363-6 SLP_S4# RUNON_1.5VS SHDN BYP R1117 100K_0402_1% SYSON# SYSON# Q13A SYSON D S R1113 1K_0402_5% SUSP SUSP Q13B SUSP# SUSP# 2 G VOUT=1.25(1+R912/R913) VOUT=1.25(1+100k/215k)=1.83V +VCCP +1.5VS +3VS +1.5V H6 HOLEA H7 HOLEA H8 HOLEA H9 HOLEA H10 HOLEA H5 HOLEA H4 HOLEA H3 HOLEA 1 +5VS H2 HOLEA H1 HOLEA Discharge circuit C1406 0.1U_0402_25V4K Q44 2N7002_SOT23-3 SUSP R1116 0_0402_5% 2 G916-390T1UF_SOT23-5 100K_0402_5% 100K_0402_5% 2N7002DW-7-F_SOT363-6 R640 C R1114 47K_0402_1% 2N7002DW-7-F_SOT363-6 @ R1115 0_0201_5% R639 OUT GND C1407 10U_0805_10V4Z 2 2 IN AO4466_SO8 330K_0402_5% 2 1 U47 C294 0.1U_0402_16V4Z +3VL +3VL C1405 10U_0805_10V4Z S S S G C1404 0.1U_0402_16V4Z D D D D +1.8V U34 10U_0805_10V4Z +3VALW +1.5VS C766 +5VS_LED Q15 SI2301BDS-T1-E3_SOT23-3 Q35 2N7002_SOT23-3 G C765 C758 0.1U_0402_16V4Z DIM_LED# 0.1U_0402_16V4Z B+ D Q34B DIM_LED# +1.5V R637 10K_0402_5% G C65 4700P_0402_25V7K +1.5V to +1.5VS Transfer R647 C764 R638 01/03 Sparate+5VS and +3VS power timing 2N7002DW-7-F_SOT363-6 1 C763 S Q34A C 470_0402_5% SUSP R224 470_0402_5% SUSP SI2301BDS-T1-E3_SOT23-3 RUNON +5VALW_LED Q33 10U_0805_10V4Z S S S G AO4466_SO8 R636 330K_0402_5% D D D D 1 C759 10U_0805_10V4Z 1 C762 10U_0805_10V4Z 0.1U_0402_16V4Z 2 330K_0402_5% C761 AO4466_SO8 G 10U_0805_10V4Z R223 S S S G D C760 D +5VALW U33 D D D D S U32 DIM LED +3VALW to +3VS Transfer +5VS B+ 2 +0.75V 1 2 Q12B SUSP Q12A SYSON# H16 HOLEA H17 HOLEA FM1 H18 HOLEA FM2 H19 H20 H11 HOLEC HOLEC HOLEA FM3 1 1 1 1 470_0402_5% 2N7002DW-7-F_SOT363-6 Q9B SUSP H15 HOLEA R646 470_0402_5% 2N7002DW-7-F_SOT363-6 Q9A SUSP R643 470_0402_5% 4 Q6B SUSP R645 470_0402_5% 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 Q6A SUSP R644 470_0402_5% 2N7002DW-7-F_SOT363-6 R642 470_0402_5% 2N7002DW-7-F_SOT363-6 R641 1 B B FM4 A A Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/07/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc DC/DC Interface Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Saturday, July 18, 2009 Sheet 36 of 45 A B C D +3VALW PQ3 TP0610K-T1-E3_SOT23-3 +3VL BATT connect to KBC pin97 AC_LED# 340K_0402_1% PR1 2 PC5 1000P_0402_50V7K 2 PC3 1000P_0402_50V7K PC4 100P_0402_50V8J 1 PC2 100P_0402_50V8J PJP1 @PJSOT24C_SOT23-3 105K_0402_1% PR6 PL2 SMB3025500YA_2P ADPIN PD1 + - PU1A LM358ADT_SO8 PR5 10K_0402_5% P PL1 SMB3025500YA_2P BATT_OVP G PR3 10K_0402_5% +DOCKVIN VIN RLZ3.6B_LL34 0.01U_0402_25V7K PC6 2 ADP_SIGNAL @1000P_0402_50V7K 499K_0402_1% PR4 PD4 PR2 10K_0402_5% ACES_88334-057N PR8 2K_0402_5% 1 ADP_ID PC12 +5VALW 2 0.01U_0402_25V7K PC1 PR9 100K_0402_5% VMB PD2 @SM05_SOT23 PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C EC_SMD EC_SMC PC8 1000P_0402_50V7K PC9 0.01U_0402_50V4Z PR7 604K_0402_1% +5VS 2 CPU SUYIN_200275MR008GXOLZR 1 1 3 GND GND 10 BATT PL3 HCB2012KF-121T50_0805 PL4 HCB2012KF-121T50_0805 PJP2 PR14 100_0402_5% PD3 @SM24.TC_SOT23-3 PH1 10K_TH11-3H103FT_0603_1% - 2 PR15 150K_0402_1% S D S P PQ1 SSM3K7002FU_SC70-3 G PU1B LM358ADT_SO8 PC11 1000P_0402_50V7K ENTRIP2 PR17 1K_0402_5% PQ2 @SSM3K7002FU_SC70-3 G BATT_TEMP PR12 2.49K_0402_1% PR11 150K_0402_1% 1 PC10 0.22U_0603_10V7K +3VL PR16 6.49K_0402_1% + 1 +5VALW D G SMB_EC_CK1 EN0_TRIP PR10 200K_0402_1% SMB_EC_CK1 BAT_ID SMB_EC_DA1 SMB_EC_DA1 2 PR13 100_0402_5% 4 Compal Secret Data Security Classification Issued Date 2007/05/29 Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title Compal Electronics, Inc DC Connector/CPU_OTP Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Sheet Saturday, July 18, 2009 D 37 of 45 A B C P4 D B+ BATT VIN P2 DH_CHG 25 LX_CHG 24 REGN 23 DL_CHG DPMDET 1 2 1 2 CELLS 20 19 18 BAT_ID PC122 @0.1U_0603_25V7K PR121 200K_0402_1% IREF PR120 133K_0402_1% BATT S 17 16 21 47K_0402_5% PR119 G PR122 681K_0402_1% 2 2 BQ24740VREF D PQ111 SSM3K7002FU_SC70-3 PC118 0.1U_0402_10V7K 1U_0603_10V6K PR117 100K_0402_5% PC121 100P_0402_50V8J PC120 0.22U_0603_10V7K 2 PC123 0.1U_0402_10V7K 1VIN_1 PR124 1K_0402_5% VIN S PACIN 1 O LM393DG_SO8 G PR134 10K_0402_5% PD103 RLZ4.3B_LL34 2 P - FSTCHG# STD_ADP PR136 60.4K_0402_1% D VIN_1 PQ113 SSM3K7002FU_SC70-3 G FSTCHG 1.24VREF PR133 10K_0603_0.1% PU102B PU102A LM393DG_SO8 PC126 0.047U_0402_16V7K + PQ112 SSM3K7002FU_SC70-3 PR127 10K_0402_1% D G PR132 100K_0402_5% 1 PR130 2.15K_0402_1% PR128 10K_0402_5% 1 PR129 10K_0402_1% 2 CHGEN# PC125 0.1U_0603_25V7K PR126 100K_0402_1% +3VL ACIN 1 +3VL P G O PQ110 PC119 PC135 470P_0603_50V8J VIN SRP SRN BAT IADAPT PR118 10K_0402_5% ADP_I PGND IADAPT 15 2 PR116 15K_0402_1% SRSET ISYNSET PR115 100K_0402_1% PR135 10K_0603_0.1% FDS6690AS_NL_SO8 22 +3VL PR131 133K_0402_1% - 2 LODRV EXTPWR PR123 1M_0402_5% PR125 47_1206_5% + PR141 4.7_1206_5% 1 REGN BATT PR112 0.015_1206_1% 2 VADJ 1 14 PD104 1SS355_SOD323-2 PL102 10U_LF919AS-100M-P3_4.5A_20% PC114 4.7U_0805_25V6-K PH PQ106 DTC115EUA_SC70-3 VDAC VIN 0.1U_0402_10V7K HIDRV PQ108 AO4466_SO8 PC113 4.7U_0805_25V6-K 12 13 VIN ACOFF PC131 @1000P_0402_50V7K 26 PC111 PC136 4.7U_0805_25V6-K BST_CHG PC116 4.7U_0805_25V6-K 27 PC115 4.7U_0805_25V6-K CHGEN PU101 BQ24740RHDR_QFN28_5X5 28 PD102 Charge Detector PC134 1000P_0402_50V7K PC129 470P_0402_50V7K PC130 270P_0402_50V7K ACP ACN BTST PC110 1U_0805_25V6K RLS4148_LL34-2 PC117 1U_0603_10V6K PC105 4.7U_0805_25V6-K 2 ACDET PVCC AGND 29 +3VL VADJ PR113 143K_0402_1% PR114 @0_0402_5% 2 PC103 4.7U_0805_25V6-K CHG_B+ SSM3K7002FU_SC70-3 TP VIN PR105 10K_0402_5% PR108 10_1206_5% IADSLP VREF PR103 47K_0402_5% ACOFF# 10 PC104 4.7U_0805_25V6-K BQ24740VREF ACSET PC112 11 VCTRL PC109 @0.1U_0603_25V7K CHGEN# LPREF 1U_0603_6.3V6M 1SS355_SOD323-2 2 PC128 @180P_0402_50V8J PQ109 S CHG_B+ PC124 0.1U_0603_25V7K PD101 ACOFF# D G PACIN PR111 3K_0402_1% PR140 100K_0402_5% PR110 0_0402_5% SUSP# PR109 150K_0402_5% PL101 HCB2012KF-121T50_0805 2 PACIN_1 ACSET PC107 @0.01U_0402_16V7K PR106 200K_0402_5% 1 PC106 0.1U_0603_25V7K 1 PQ105 DTC115EUA_SC70-3 PC102 1U_0603_6.3V6M PC108 0.1U_0603_25V7K AC_SET S PC133 470P_0402_50V7K ACDET PR104 0_0402_5% PQ104 DTA144EUA_SC70-3 D PR102 0.012_2512_1% 2 PQ107 SSM3K7002FU_SC70-3 G PQ103 SI4459ADY PR101 47K_0402_5% PC101 47P_0402_50V8J PR107 47K_0402_1% PQ101 SI4835DDY-T1-E3_SO8 LPMD PC132 @1000P_0402_50V7K PQ102 FDS6675BZ_SO8 S PU104 PC127 2 1.24VREF ANODE NC LMV431ACM5X_SOT23-5 Compal Secret Data Security Classification Issued Date 2007/05/29 Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C Compal Electronics, Inc Charger Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: A CATHODE NC 22P_0402_50V8J 100K_0402_1% PR138 PR137 20K_0402_1% REF 1 ACDET Saturday, July 18, 2009 D Sheet 38 of 45 A B C D E S 10U_1206_25V6M PC305 PC317 0.1U_0402_25V6 1 + PC310 150U_D_6.3VM TPS51125RGER_QFN24_4X4 +5VALWP 18 EN0 13 UG1_5V LG_5V PL303 10U_LF919AS-100M-P3_4.5A_20% PR316 4.7_1206_5% 19 DRVL2 PC315 680P_0603_50V7K PC311 10U_0805_10V6K 1 VL PR311 191K_0402_1% EN0_TRIP PQ306 SSM3K7002FU_SC70-3 S PC304 2200P_0402_50V7K DRVL1 LL2 12 PR309 1M_0402_1% ENTRIP1 D VFB1 LL1 LX_5V VCLK UG_5V 20 VREG5 21 11 2VREF_51125 G ENTRIP1 VREF VBST1 DRVH1 B++ G PR308 PC308 2.2_0402_5% 0.1U_0402_10V7K BST_5V 2 DRVH2 ENTRIP2 D PQ305 SSM3K7002FU_SC70-3 23 VBST2 PGOOD 10 B++ PC314 @680P_0603_50V7K 2 + PC309 220U_6.3VM_R15 24 PQ302 AO4466_SO8 PR315 @4.7_1206_5% LG_3V VO1 22 VIN UG_3V VREG3 PR306 140K_0402_1% 17 PC307 0.1U_0402_10V7K LX_3V GND BST_3V B++ PQ304 FDS6690AS_NL_SO8 PR318 0_0805_5% PC312 0.1U_0603_25V7K +3VALWP PR307 2 0_0402_5% VO2 16 15 AO4932_2N_SO8 PL302 3.3UH_SIQB74B-4R7PF_5.9A_20% P PAD TONSEL 25 VFB2 PU301 UG1_3V 1G 1S/2D 1S/2D 1S/2D ENTRIP2 D1 D1 G2 S2 PC306 10U_0805_6.3V6M PC303 4.7U_0805_25V6-K PC301 2200P_0402_50V7K PQ301 PR305 100K_0402_1% ENTRIP1 PR304 20K_0402_1% ENTRIP2 PR303 20K_0402_1% +3VLP PC316 0.1U_0402_25V6 PR302 30.9K_0402_1% SKIPSEL PL301 HCB2012KF-121T50_0805 PR301 13.7K_0402_1% 14 B++ B+ 1 PC302 0.22U_0603_10V7K 2VREF_51125 R_EC_RSMRST# +5VL VL PJP304 PJP302 S VL PR313 100K_0402_5% PQ307 G SSM3K7002FU_SC70-3 +5VALWP PAD-OPEN 2x2m +5VALW (4.5A,180mils ,Via NO.= 9) +3VALWP EC_ON +3VL +3VLP PAD-OPEN 4x4m PJP303 PJP301 2 +3VALW (3A,120mils ,Via NO.= 6) PAD-OPEN 2x2m PAD-OPEN 4x4m S D 3 D 100K_0402_5% PR314 PACIN_1 PC318 @0.047U_0402_16V7K PQ308 @SSM3K7002FU_SC70-3 2 G PR317 @604K_0402_1% 1 Compal Secret Data Security Classification 2007/05/29 Issued Date Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc 3.3VALWP/5VALWP Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Saturday, July 18, 2009 Sheet E 39 of 45 A B C D 1 PR401 0_0402_5% PL401 VOUT V5FILT PC406 @680P_0402_50V7K DRVH 13 DH_1.05V LX_1.05V LL 12 TRIP 11 V5DRV 10 PR411 0_0402_5% 14 PQ401 AO4466_SO8 PL402 2.2UH_PCMC063T-2R2MN_8A_20% +5VALW PR406 15.4K_0402_1% PR407 4.7_1206_5% + 2 PC415 4.7U_0805_10V6K DRVL +1.05V_VCCP PC412 220P_0603_50V8J PQ402 FDS6690AS_NL_SO8 DL_1.05V TPS51117RGYR_QFN14_3.5x3.5 PGND PGOOD +1.05V_VCCP PR408 10.5K_0402_1% VFB GND PC409 1U_0603_10V6K B+ 2200P_0402_50V7K PC405 4.7U_0805_25V6-K PC404 1 4.7U_0805_25V6-K PC403 PC402 0.1U_0402_10V7K PC408 220U_6.3VM_R15 TON VBST TP EN_PSV 2 0_0402_5% 15 PU401 PR404 255K_0402_1% PR405 +1.05V_VCCP BST1_1.05V1 PR402 0_0402_5% PR403 316_0402_1% 2 BST_1.05V 0.1U_0402_25V6 PC414 +5VALW PC401 @1000P_0402_50V7K HCB1608KF-121T30_0603 1.05V_B+ PR410 @10K_0402_5% 2,36,38> SUSP# PR409 25.5K_0402_1% 3 PJP401 +1.05V_VCCP +VCCP (6A,240mils ,Via NO.=12) PAD-OPEN 4x4m 4 Compal Secret Data Security Classification Issued Date 2007/05/29 Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title Compal Electronics, Inc 1.05V_VCCP Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Sheet Saturday, July 18, 2009 D 40 of 45 D D B+++ PR521 SYSON PC524 @1000P_0402_50V7K V5FILT VFB PGOOD LX_1.5V 1 PC521 0.1U_0402_25V6 2 C TRIP 11 V5DRV 10 DRVL UG1_1.5V 2200P_0402_50V7K PC505 UG_1.5V 12 PC504 4.7U_0805_25V6-K 14 TP VBST 13 LL PR515 13.7K_0402_1% +5VALW LG_1.5V DRVH +1.5VP PL501 2.2UH +-20% PCMC063T-2R2MN 8A +5VALW PC523 4.7U_0805_10V6K PQ503 FDS6690AS_SO8 PC519 @680P_0603_50V7K + PC508 2 +1.5V PC510 4.7U_0805_6.3V6K 330U_2V_M_R15M PR516 @4.7_1206_5% TPS51117RGYR_QFN14_3.5x3.5 PR502 10K_0603_0.1% 1 7 PC522 1U_0603_10V6K PR501 10.2K_0603_0.1% +1.5VP VOUT PQ501 AO4466_SO8 PR522 316_0402_1% PR508 0_0402_5% 2 +5VALW 0_0402_5% PGND +5VALW PR520 GND +1.5VP TON C EN_PSV PU502 PR523 255K_0402_1% 2 15 PR510 PC511 0_0402_5% 0.1U_0402_10V7K BST_1.5V 2 PC516 4.7U_0805_25V6-K 0_0402_5% B+ PL502 HCB1608KF-121T30_0603 1 PR503 @10K_0402_5% B B DDR3_SM_PWROK PJP501 PAD-OPEN 4x4m PJP502 +1.5VP +1.5V (8A,320mils ,Via NO.= 16) PAD-OPEN 4x4m A A Compal Secret Data Security Classification 2007/05/29 Issued Date Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc 1.5VP Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Saturday, July 18, 2009 Sheet 41 of 45 D D +1.5V VCNTL GND NC VREF NC VOUT NC TP +5VALW PR601 1K_0402_1% 1 VIN 2 PC602 @10U_0805_10V4Z PC601 10U_0805_10V4Z PU601 PC603 1U_0603_16V6K G2992F1U_SO8 C +0.75VP S G PR603 1K_0402_1% PR604 0_0402_5% SUSP D PQ601 SSM3K7002FU_SC70-3 1 PR602 @0_0402_5% PC604 0.1U_0402_16V7K SYSON# PC605 10U_0805_6.3V6M C PC606 @0.1U_0402_16V7K PJP601 +0.75VP +0.75V (2A,80mils ,Via NO.= 4) PAD-OPEN 3x3m B B A A Compal Secret Data Security Classification Issued Date 2006/11/23 Deciphered Date 2007/11/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc 0.75VP Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Sheet Saturday, July 18, 2009 42 of 45 +5VS NTC SOFT PQ204 RQW130N03_PSO8 28 PHASE_CPU2 UGATE2 27 UGATE_CPU2-1 BOOT2 26 NC 25 BOOT_CPU2 PR227 2.2_0603_5% PC217 0.22U_0603_10V7K PU201 4 270P_0402_50V7K 100P_0402_50V8J PR239 10_0603_5% PC224 2200P_0402_50V7K B PR238 3 +5VS PC240 2200P_0402_50V7K PC208 1000P_0402_50V7K PC241 PC239 68U_25V_M_R0.44 68U_25V_M_R0.44 PC243 47P_0402_50V8J 2 PC207 2200P_0402_50V7K PC206 4.7U_0805_25V6-K PC205 4.7U_0805_25V6-K PC233 4.7U_0805_25V6-K PC234 4.7U_0805_25V6-K 1 PR220 10K_0402_1% 2 PC244 47P_0402_50V8J C 0.36UH_PCMC104T-R36MN1R17_30A_20% PL203 PQ206 FDS8672S_SO8 1_0402_5% PR233 VSUM PR232 @0_0603_5% PC223 0.22U_0603_10V7K VCC_PRM ISEN2 CPU_B+ B PC225 0.1U_0603_25V7K 2 PR240 1K_0402_1% PQ205 FDS8672S_SO8 PR234 1_0603_5% PC221 1U_0402_6.3V6K CPU_B+ PC226 330P_0603_50V8 VSUM PC228 0.01U_0603_50V7K PC231 0.22U_0603_10V7K PR244 3.57K_0402_1% PC230 0.1U_0402_16V7K 2 10KB_0603_5%_ERTJ1VR103J PH201 VCC_PRM 2 PR243 1K_0402_1% PR242 PC229 180P_0402_50V8J 11K_0402_1% VSSSENSE PR241 PC227 330P_0603_50V8 2 VCCSENSE 2.61K_0402_1% 100_0402_1% 1 2 PR237 1K_0402_1% PC222 PR236 @0_0402_5% PC218 1000P_0402_50V7K PR235 97.6K_0402_1% PC220 2 +VCC_CORE UGATE_CPU2-2 PR229 4.7_1206_5% PR246 4.7_1206_5% PC219 2200P_0603_50V7K PR225 0_0603_5% 2 24 ISEN1 29 ISEN2 PGND2 PHASE2 ISEN1 ISEN2 PC212 4.7U_0805_25V6-K LGATE_CPU2 30 31 PVCC LGATE2 23 VDD 22 GND 21 VIN 20 VSUM 19 VO 18 DROOP DFB 17 16 FB2 RTN 12 15 FB 13 COMP 11 VSEN 1000P_0402_50V7K PC216 PR228 13K_0402_1% 10 VDIFF 13K_0402_1% VW 14 PR226 OCSET D PC245 47P_0402_50V8J LGATE_CPU1 32 LGATE1 + PC238 47P_0402_50V8J VR_TT# VR_TT# 0.022U_0603_25V7K PC215 2 VCC_PRM ISEN1 0.22U_0603_10V7K PC236 4.7U_0805_25V6-K 33 PC214 2200P_0402_50V7K PC235 4.7U_0805_25V6-K PGND1 PR231 10K_0402_1% RBIAS PC213 4.7U_0805_25V6-K PR223 1_0402_5% PR224 @0_0603_5% PC211 VSUM PQ203 FDS8672S_SO8 PHASE1 PMON PQ202 FDS8672S_SO8 PHASE_CPU1 PR219 3.65K_0805_1% UGATE_CPU1-1 34 PR230 3.65K_0805_1% 35 3 36 BOOT1 UGATE1 ISL6266ACRZ-T_QFN48_7X7 + PL202 0.36UH_PCMC104T-R36MN1R17_30A_20% PR218 4.7_1206_5% 2 PR245 PC210 4.7_1206_5% 2200P_0603_50V7K PR221 @0_0402_5% PR222 147K_0402_1% C 1 0_0603_5% PR217 VID0 VID1 VID2 VID3 8 37 38 39 40 41 VID4 VID5 PC204 68U_25V_M_R0.44 PC242 470P_0402_50V7K 1 1 2 PR213 PR205 PR212 PR211 PR210 PR209 42 45 46 47 43 VID6 VR_ON DPRSLPVR 3V3 PSI# CLK_EN# PGOOD + PC237 470P_0402_50V7K CPU_VID2 CPU_VID1 CPU_VID0 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 VR_ON 2.2_0603_5% 0.22U_0603_10V7KUGATE_CPU1-2 PR214 PC209 2 49 GND 1 PC201 1U_0603_6.3V6M PR216 H_PSI# DPRSTP# PC203 2.2U_0603_6.3V6K PQ201 BOOT_CPU1 VGATE PL201 SMB3025500YA_2P RQW130N03_PSO8 @499_0402_1% 1.91K_0402_1% PR215 +3VS 0_0402_5% 48 PR206 0_0402_5% PC202 0.022U_0402_16V7K 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% PR204 44 H_DPRSTP# 0_0402_5% PR207 PR203 CLK_ENABLE# +3VS 499_0402_1% DPRSLPVR PR208 PR201 D B+ CPU_B+ PR202 1_0603_5% PC232 0.22U_0402_6.3V6K 1 A A Compal Electronics, Inc Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom Date: Rev 1.0 Saturday, July 18, 2009 Sheet 43 of 45 A B C D E Version Change List ( P I R List ) for Power Circuit Item Page# 1 37 40 41 Title 3.3VALWP/5VALWP Date Request Owner Issue Description Rev Solution Description Add PC316, PC317 5/4 Compal RF solution +1.05V_VCCP 5/4 Compal RF solution Add PC414 +1.5VP 5/4 Compal RF solution Add PC521 2 3 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc Power Changed-List History-1 Size Document Number Custom Montevina Date: Rev 1.0 Blade UMA LA4105P Saturday, July 18, 2009 Sheet E 44 of 45 Item Fixed Issue (Reason for change) PAGE Modify List Date Phase 85 DDR2 change to DDR3 09 V_DDR_MCH_REF change to +1.5V 03/31 1.4DB 86 DDR2 change to DDR3 09 SMRCOMP_VOH change to +1.5V 03/31 1.4DB 87 DDR2 change to DDR3 09 SMRCOMP change to +1.5V 03/31 1.4DB 88 DDR2 change to DDR3 09、41 Add AND gate (U48) and R1119~R1120, C1408 for SM_RWOK 03/31 1.4DB 89 DDR2 change to DDR3 12 VCC_SM_CK change to +1.5V 03/31 1.4DB 90 DDR2 change to DDR3 13 VCC_SM change to +1.5V 03/31 1.4DB 91 DDR2 change to DDR3 15、16 Change to DDR3 SODIMM 03/31 1.4DB 36 Delete reserve +1.8V DC-DC, and add +1.5V DC-DC 03/31 1.4DB D D 92 DDR2 change to DDR3 93 DDR2 change to DDR3 36 Add LDO for +1.8V_LVDS 03/31 1.4DB 94 DDR2 change to DDR3 27 delete +1.8VS_CR, card reader internal LDO can provide +1.8VS 03/31 1.4DB Gobi RF test and UTX for debug card 26 modify R750 netname trace, add R1129 for UTX 06/19 1.4PVR EMI solution for ENE cap board 32 modify R731 and R732 to 33 ohm BOM change 06/19 1.4PVR EMI solution for ENE cap board 33 modify R234 ,R56 and R149 to 33 ohm , C310 to 15pF BOM change 06/19 1.4PVR C C B B A A Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/07/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc HW PIR Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Saturday, July 18, 2009 Sheet 45 of 45 ... Classification 2007/08/28 Issued Date 43154432L01： ： UMA GM PA FF (V) 43154432L02： ： UMA GM PR FF (V) 43154432L03： ： UMA GL PR FF43154432L04： ： UMA GM OPP (V) ： UMA GL OPP 43154432L05： ：SA00001P930 (SI-1、... Compal Electronics, Inc Block Diagram Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet E of 45 A Symbol Note : Voltage Rails O MEANS ON USB assignment:... Compal Electronics, Inc Notes List Size Document Number Custom Montevina Blade Date: Rev 1.0 UMA LA4105P Saturday, July 18, 2009 Sheet of 45 60mA 50mA 25mA 1A D +V_BATTERY Dock 35mA 177mA INVPWR_B+