CUSTOMER EDUCATION SERVICES HSPICE Advanced Topics Workshop Student Guide 60-I-032-BSG-005 2007.03 Synopsys Customer Education Services 700 East Middlefield Road Mountain View, California 94043 Workshop Registration: 1-800-793-3448 www.synopsys.com Copyright Notice and Proprietary Information Copyright 2007 Synopsys, Inc All rights reserved This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the 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Netlist Structure 1-6 Netlist Structure: Overview 1-7 Netlist Structure: Topology 1-8 Node Naming Conventions (1/2) 1-9 Node Naming Conventions (2/2) 1-10 Element Naming Conventions 1-11 Units and Scale Factors 1-12 MEASURE 1-13 MEASURE: Rise/Fall (1/2) 1-14 MEASURE: Rise/Fall (2/2) 1-15 MEASURE: AVG, RMS, MIN, MAX, PP (1/2) 1-16 MEASURE: AVG, RMS, MIN, MAX, PP (2/2) 1-17 MEASURE: FIND-WHEN 1-18 MEASURE: FIND-WHEN Examples 1-19 MEASURE: Equation Evaluation 1-20 MEASURE: Derivative Function 1-21 MEASURE: Integral Function 1-22 ALTER: Description 1-23 ALTER: Limitations 1-24 ALTER Rules (1/2) 1-25 ALTER Rules (2/2) 1-26 ALTER: Example 1-27 Discovery AMS Simulation Interface Basics 1-28 Discovery AMS Simulation Interface 1-29 Synopsys 60-I-032-BSG-005 i HSPICE Advanced Topics Table of Contents Discovery AMS Simulation Interface – Project Management 1-30 Discovery AMS Simulation Interface – Project Management 1-31 Discovery AMS Simulation Interface – Setup 1-32 Discovery AMS Simulation Interface – Netlist & Simulation 1-33 Discovery AMS Simulation Interface – Netlist & Simulation 1-34 Discovery AMS Simulation Interface – HSPICE Setup 1-35 Discovery AMS Simulation Interface – HSPICE Setup 1-36 Discovery AMS Simulation Interface – Run 1-37 Discovery AMS Simulation Interface – Run 1-38 Discovery AMS Simulation Interface - Output 1-39 Discovery AMS Simulation Interface - Simulation 1-40 Invoking CosmosScope 1-41 CosmosScope Basics 1-42 CosmosScope Pulldown Menu Bar 1-43 CosmosScope Icon Bar 1-44 CosmosScope Tool Bar 1-45 CosmosScope Mouse Usage 1-46 Opening a Plotfile 1-47 CosmosScope File/Signal Control Forms 1-48 Scope Plotting Techniques (1/2) 1-49 Scope Plotting Techniques (2/2) 1-50 CosmosScope Measurements 1-51 CosmosScope Measurements 1-52 CosmosScope Measurements 1-53 CosmosScope Calculator 1-54 Using the Calculator 1-55 Lab 1: HSPICE 1-56 Unit 2: Verilog-A Modules Unit Objectives 2-2 Introduction to Verilog-A 2-3 Feature Overview (1/2) 2-4 Feature Overview (2/2) 2-5 Verilog-A Usage Overview 2-6 Loading Verilog-A Files (1/2) 2-7 Loading Verilog-A Files (2/2) 2-8 Defining the Verilog-A Module Path 2-9 Instantiation Syntax 2-10 Verilog-A Model Cards 2-11 Instantiation Examples (1/2) 2-12 Instantiation Examples (2/2) 2-13 Parameter Case Sensitivity 2-14 Synopsys 60-I-032-BSG-005 ii HSPICE Advanced Topics Table of Contents Bus Support 2-15 Output Control (1/2) 2-16 Output Control (2/2) 2-17 Output Control Example (1/2) 2-18 Output Control Example (2/2) 2-19 Overriding Subcircuits with Verilog-A Modules 2-20 Disabling option VAMODEL with option SPMODEL 2-21 Addition Information – vamodel and spmodel 2-22 Stand-Alone Compiler 2-23 Verilog-A Examples 2-24 Lab 2: Verilog-A Modules 2-25 Unit 3: Simulating Variability - Design for Yield Unit Objectives 3-2 Wafer Yield in Nanometer Technologies 3-3 Variation Components Across Wafer 3-4 Variation Components From Reticle 3-5 Variation Components Due To Discreteness of Atoms and Photons 3-6 Variation Components Due To Proximity: (not random) 3-7 Quantifying Variability in Nanometer Technologies 3-8 Contents 3-9 Cu Interconnect Stack Structure 3-10 Random Variation in Interconnect 3-11 Interconnect Variation Modeling: Current Approach 3-12 Interconnect Variation Modeling: Statistical Extraction Flow 3-13 Contents 3-14 Variation Model in HSPICE 3-15 Variation Block Overview 3-16 Variation Block Structure 3-17 Options and Common Parameters 3-18 Independent Random Variables 3-19 Dependent Random Variables 3-20 Syntax for Specifying Variations 3-21 Variations on Model and Element Parameters 3-22 Simple Variation Block Example 3-23 Principal Components Based Global Variation Modeling 3-24 Local Variations in Nanometer Technologies 3-25 Spatial Variation Example 3-26 Designer’s Variation Block 3-27 Variation Block Summary 3-28 Contents 3-29 Monte Carlo Analysis in HSPICE 3-30 Synopsys 60-I-032-BSG-005 iii HSPICE Advanced Topics Table of Contents Monte Carlo Commands 3-31 Options for Monte Carlo Analysis 3-32 Factorial Sampling 3-33 One-Factor-At-a-Time Sampling 3-34 Latin Hypercube Sampling 3-35 Monte Carlo Analysis Flow 3-36 Monte Carlo Result Distributions 3-37 Monte Carlo Convergence 3-38 Contents 3-39 Interpreting Results of Monte Carlo 3-40 Data Mining: Pairs Plot 3-41 Data Mining: Pareto Plot 3-42 Monte Carlo Analysis Summary 3-43 Contents 3-44 Mismatch Analysis 3-45 Mismatch 3-46 Effects of Mismatch on DC Amplifier 3-47 HSPICE DCMatch Analysis Overview 3-48 DCMatch Analysis Command 3-49 DCMatch Table Result Example 3-50 Amplifier with Rail-to-Rail Input Range 3-51 DCMatch Simulation Result 3-52 Benefits of DCMatch Analysis 3-53 HSPICE ACMatch Analysis Overview 3-54 ACMatch Analysis Command 3-55 Fully Differential Amplifier 3-56 Power Supply Feedthrough 3-57 Benefits of ACMatch Analysis 3-58 Contents 3-59 Mismatch Versus Monte Carlo Analysis 3-60 DCMatch and ACMatch Versus Monte Carlo 3-61 HSPICE Documentation on Variability 3-62 References 3-63 Presentation for Modeling Engineers 3-64 Lab 3: Simulating Variability – Design for Yield 3-65 Unit 4: S-Parameters and Linear Analysis Unit Objectives 4-2 S-Parameter Basics 4-3 Two-Port Scattering Parameters 4-4 Linear Multi-Port Parameter Analysis 4-5 Linear Characterization 4-6 Synopsys 60-I-032-BSG-005 iv HSPICE Advanced Topics Table of Contents Port (P) Element 4-7 Port Element Syntax 4-8 LIN Analysis Syntax 4-9 LIN Keywords 4-10 HSPICE Linear Characterization 4-11 LIN Parameter Definitions (1/4) 4-12 LIN Parameter Definitions (2/4) 4-13 LIN Parameter Definitions (3/4) 4-14 LIN Parameter Definitions (4/4) 4-15 Introduction to Noise Analysis (1/3) 4-16 Introduction to Noise Analysis (2/3) 4-17 Introduction to Noise Analysis (3/3) 4-18 Noise Representation (1/2) 4-19 Noise Representation (2/2) 4-20 Noise Types (1/3) 4-21 Noise Types (2/3) 4-22 Noise Types (3/3) 4-23 Noise Calculation Example 4-24 S-Element 4-25 S-Element Syntax 4-26 S-Element Rules 4-27 S-Element Keywords (1/4) 4-28 S-Element Keywords (2/4) 4-29 S-Element Keywords (3/4) 4-30 S-Element Keywords (4/4) 4-31 S-Element Keywords (5/5) 4-32 S-Parameter Model Syntax 4-33 SP Model Syntax 4-34 SP Model Keywords (1/3) 4-35 SP Model Syntax (2/3) 4-36 SP Model Syntax (3/3) 4-37 SP Model Example 4-38 Using S-Parameters Example 4-39 Mixed Mode S-Parameters 4-40 Mixed Mode Port Element 4-41 Extracting Mixed-Mode S-Parameters (1/3) 4-42 Extracting Mixed-Mode S-Parameters (2/3) 4-43 Extracting Mixed-Mode S-Parameters (3/3) 4-44 Mixed Mode S-Parameter Example 4-45 Mixed-Mode S-Parameter Example Results (1/2) 4-46 Mixed-Mode S-Parameter Example Results (2/2) 4-47 Using Mixed Mode S-Parameters (1/2) 4-48 Using Mixed Mode S-Parameters (2/2) 4-49 Lab 4: Using LIN and S-Parameters 4-50 Synopsys 60-I-032-BSG-005 v HSPICE Advanced Topics Table of Contents Unit 5: Transmission Lines and Field Solver Unit Objectives 5-2 Introduction to Transmission Lines 5-3 Transmission Lines (1/4) 5-4 Transmission Lines (2/4) 5-5 Transmission Lines (3/4) 5-6 Transmission Lines (4/4) 5-7 Transmission Lines in HSPICE 5-8 Ideal Transmission Lines: T-Element (1/2) 5-9 Ideal Transmission Lines: T-Element (2/2) 5-10 W-Element Transmission Line 5-11 Comparison of U vs W-Elements 5-12 W-Element 5-13 W-Element RLGC Matrices 5-14 RLGC File 5-15 W-Element Accepts U-Model 5-16 W-Element Syntax 5-17 W-Element Keywords 5-18 Benefits of DELAYOPT 5-19 Optimal Number Of W-Element Segments 5-20 AC vs TRAN Comparison At 1GHz 5-21 AC vs TRAN Comparison At 5GHz 5-22 AC vs TRAN Comparison At 20GHz 5-23 Using S-Parameters in Transmission Lines 5-24 Using S-Parameters in W-Element Keywords 5-25 Using S-Parameters in W-Element Syntax 5-26 Using S-Parameters In W-element Guidelines 5-27 W-Element Thermal Noise Modeling 5-28 Thermal Noise Model Keywords 5-29 W-Element with Thermal Model Syntax 5-30 Field Solver 5-31 Filament Method 5-32 Modeling Geometry Basics 5-33 What Input does the Field Solver Require? 5-34 MATERIAL Definition 5-35 Layerstack Rules 5-36 LAYERSTACK 5-37 SHAPE 5-38 FSOPTIONS 5-39 Field Solver Model (1/2) 5-40 Field Solver Model (2/2) 5-41 Synopsys 60-I-032-BSG-005 vi HSPICE Advanced Topics Table of Contents Field Solver Model Rules (1/2) 5-42 Field Solver Model Rules (2/2) 5-43 Field Solver Example 5-44 Partial Netlist for Field Solver Example 5-45 Modeling Coaxial Lines 5-46 Coaxial Line Example 5-47 Shielded Twin Lead Example 5-48 Lab 5: Transmission Lines and Field Solver 5-49 Unit 6: IBIS Unit Objectives 6-2 What is IBIS? 6-3 IBIS Model Characteristics 6-4 IBIS Buffers 6-5 IBIS Buffer Block Diagram 6-6 Buffer Output Model 6-7 IBIS Model I-V Curves (1/2) 6-8 IBIS Model I-V Curves (2/2) 6-9 IBIS I-V Curve Rules of Thumb 6-10 Ramp and V-t Curve Measurements 6-11 Schematic of an I/O Circuit 6-12 IBIS Buffer Basic Syntax 6-13 Supported Buffer Types and Syntax (1/2) 6-14 Supported Buffer Types and Syntax (2/2) 6-15 BUFFER Keyword 6-16 BUFFER Keyword Example 6-17 TYP Keyword 6-18 Power On | Off 6-19 INTERPOL and NOWARN Keywords 6-20 XV_PU and XV_PD Keywords 6-21 RAMP_FWF and RAMP_RWF Keywords 6-22 FWF_TUNE and RWF_TUNE Keywords 6-23 C_Comp 6-24 IBIS Buffer Scaling Keywords 6-25 HSP_VER Keyword 6-26 Using the IBIS Command (1/2) 6-27 IBIS Command Syntax (2/2) 6-28 IBIS Command Syntax (1/2) 6-29 IBIS Command Syntax (2/2) 6-30 IBIS Command Examples 6-31 Using the PKG Command (1/2) 6-32 Using the PKG Command (2/2) 6-33 Synopsys 60-I-032-BSG-005 vii HSPICE Advanced Topics Table of Contents Using the EBD Command 6-34 EBD Command Syntax 6-35 EBD Example 6-36 EBD Example 6-37 EBD Limitations 6-38 Using the ICM Command 6-39 ICM Structure (1/2) 6-40 ICM Structure (2/2) 6-41 Additional ICM Constructs 6-42 ICM Swath 6-43 ICM Syntax 6-44 ICM Example 6-45 Multi-Lingual Model Support (1/2) 6-46 Multi-Lingual Model Support (2/2) 6-47 Example 6-48 Component Calls for [External Circuit] 6-49 Name Limit Extension 6-50 Lab 6: IBIS Buffers 6-51 Unit CS: Customer Support Synopsys Support Resources CS-2 SolvNet Online Support Offers CS-3 SolvNet Registration is Easy CS-4 Support Center: AE-based Support CS-5 Other Technical Sources CS-6 Summary: Getting Support CS-7 Synopsys 60-I-032-BSG-005 viii HSPICE Advanced Topics Multi-Lingual Model Support (1/2) Supports SPICE or Verilog-A buffer model Syntax: B_SPICE node1 node2 node3 … + file='ibis_filename' model='model_name' + [nd_in=node_input] + [nd_en=node_enable] + [nd_outofin=node_out_of_in] + [typ={typ|min|max}] [power={on|off}] + [nowarn] + [para_begin para1=value1 para2=value2 … para_end] 6- 46 IBIS HSPICE Advanced Topics © 2007 6-46 Multi-Lingual Model Support (2/2) Buffer element nodes must map port names declared in [Ports] of [External Model] The file of subcircuit listed in [Corner] of [External Model] must be manually included in netlist if the subcircuit is used by external model Keywords para_begin and para_end are used to assign values to parameters which are declared in [External Model] with Verilog-A language 6- 47 IBIS HSPICE Advanced Topics © 2007 6-47 Example bspice Dri Out Vcc Ven Rcv + file= 'extmdlva.ibs' + model= 'vatest' + nd_in=PlsV + nd_en=Vcc + nd_outofin=Oti + typ = typ + power=off ibs file(extmdlva.ibs) example ; [External Model] Language Verilog-A(MS) ; 6- 48 IBIS HSPICE Advanced Topics © 2007 6-48 Component Calls for [External Circuit] Support component calls for SPICE or Verilog-A formatted [External Circuit] [External Circuit] is used to describe either buffer (similar to [External Model]) or interconnection inside component The naming rule to probe a die node declared in Port_map of [Circuit Call] in a interconnection description: ‘cname’_’die_node_name’ 6- 49 IBIS HSPICE Advanced Topics © 2007 6-49 Name Limit Extension The limit on IBIS filenames has been extended to 44 characters from the existing 24 characters The model and signal name limit has been extended to 40 characters from the existing 20 characters 6- 50 IBIS HSPICE Advanced Topics © 2007 6-50 Lab 6: IBIS Buffers 45 minutes During this lab, you will use IBIS buffers and a transmission line to a simple signal integrity analysis IBIS buffers Transmission line Signal Integrity analysis 6- 51 IBIS HSPICE Advanced Topics © 2007 6-51 This page was intentionally left blank IBIS HSPICE Advanced Topics © 2007 6-52 Customer Support © 2007 Synopsys, Inc All Rights Reserved Customer Support © 2007 20070130 CS-1 Synopsys Support Resources Build Your Expertise: Customer Education Services www.synopsys.com Workshop schedule and registration Download materials (SolvNet id required) Empower Yourself: solvnet.synopsys.com Online technical information and access to support resources Documentation & Media Access Synopsys Experts: Support Center CS- Customer Support © 2007 CS-2 SolvNet Online Support Offers Immediate access to the latest technical information Thousands of expertauthored articles, Q&As, scripts and tool tips Enter-a-call online Support Center access Release information Online documentation License keys Electronic software downloads Synopsys announcements (latest tool, event and product information) CS- Customer Support © 2007 CS-3 SolvNet Registration is Easy Go to solvnet.synopsys.com/ ProcessRegistration Pick a username and password You will need your “Site ID” on the following page Authorization typically takes just a few minutes CS- Customer Support © 2007 CS-4 Support Center: AE-based Support Industry seasoned Application Engineers: 50% of the support staff has > years applied experience Many tool specialist AEs with > 12 years industry experience Access to internal support resources Great wealth of applied knowledge: Service >2000 issues per month Remote access and debug via ViewConnect Fastest access Contact us: Web: Enter A Call from solvnet.synopsys.com See http://www.synopsys.com/support for local support resources CS- Customer Support © 2007 CS-5 Other Technical Sources Application Consultants (ACs): Tool and methodology pre-sales support Contact your Sales Account Manager for more information Synopsys Professional Services (SPS) Consultants: Available for in-depth, on-site, dedicated, custom consulting Contact your Sales Account Manager for more details SNUG (Synopsys Users Group): www.snug-universal.org CS- Customer Support © 2007 CS-6 Summary: Getting Support Customer Education Services SolvNet Support Center SNUG CS- Customer Support © 2007 CS-7 This page was intentionally left blank Customer Support © 2007 CS-8 ... & Overview HSPICE Advanced Topics © 2007 i-3 Workshop Goal Enhance the student s use of HSPICE for statistical analysis and signal integrity applications i- Introduction & Overview HSPICE Advanced... analysis data files 1- Introduction HSPICE Advanced Topics © 2007 1-4 Starting HSPICE Typical command line invocations: hspice design.sp > design.lis (UNIX only) hspice –i design.sp -o design.lis... of HSPICE i- Introduction & Overview HSPICE Advanced Topics © 2007 i-5 Agenda: Day DAY 1 Introduction Verilog-A Modules Simulating Variability – Design for Yield i- Introduction & Overview HSPICE