AN511 PLD Replacement Author: Sumit Mitra Microchip Technology, Inc (exclusive OR.) and one AND operation will be required For example, to determine product term P3 = A3.A2.A1.A0, the expression to evaluate is: (A7:A0 XOR xxxx0011b) AND 00001111b) INTRODUCTION PIC16C5X microcontrollers are ideal for implementing low cost combinational and sequential logic circuits that traditionally have been implemented using either numerous TTL gates or using programmable logic chips such as PLAs or EPLDs The PIC16C5X is a family of high-performance 8-bit microcontrollers from Microchip Technology Inc It employs a Harvard architecture, (i.e., has a separate data bus [8-bit] and program bus [12-bit]) All instructions are single word and execute in one cycle except for program branches The instruction cycle time is 200 ns at 20 MHz PIC16C5X microcontrollers are ideal for PLD-type applications because: • Very low cost • Few external components required • Fully programmable PIC16C5X Microcontrollers are offered as One Time Programmable (OTP) EPROM devices • Available off the shelf from distributors • Calibration in software for improved measurement accuracy • Power savings using PIC16C5X’s Sleep mode • PIC16C5X’s output pins have large, current source/sink capability to drive LED’s directly IMPLEMENTING A PLA To implement a generic combinational logic function, we can simply emulate an AND-OR PLA in software This requires the logic outputs to be described as sums of products To describe our algorithm, we will use a simple 8-input, 8-output PLA with 24 product terms (Figure 1) We will further use the truth table in Figure as the PLA function being implemented In this example, only four inputs (A3:A0) are used and the other four inputs (A7:A4) are “don’t care” On the output side, seven output pins (Y6:Y0) are used and Y7 is unused To implement this PLA, the logic inputs A0,A1, ,A7 can be connected to PORTB pins RB0,RB1, ,RB7 respectively The logic outputs Y0,Y1, ,Y7 will appear on PORTC pins RC0,RC1, ,RC7 respectively PORTB is configured as input and PORTC will be configured as output To evaluate each product term one XOR 1997 Microchip Technology Inc The constant with which XOR is performed will be referred to as P3_x in our discussion P3_x = xxxx0011b will ensure that if A3:A0 = 0011b, then the least significant 4-bits of the result will be 0000b The AND constant, referred to here as P3_a (Product term 3, AND constant) basically eliminates the “don’t care” inputs (here A7:A4) by masking them Therefore, if the result of the XOR.-.AND operation is zero then P3 = else P3 = Once the Product terms are evaluated they are stored in four product registers Preg_0 to Preg_3 To determine an output term: Y0 = P0 + P2 + P3 + P5 + P6 + P7 + P8 + P9 + P10 + P12 + P13 + P14 we need to evaluate the following expression: (Preg_a AND OR_a0) OR (Preg_b AND OR_b0) OR (Preg_c AND OR_c0) In our case the constant values to implement Y0 are as follows: OR_a0 = 1 P7 P6 P5 1 P3 P2 P0 OR_b0 = 1 1 1 OR_c0 = 0 0 0 0 For a larger number of inputs, outputs, or product terms, the evaluation will be more complex but follows the same principle Appendix A shows the assembly code to implement this input x output x 24 Product PLA This example optimizes speed as well as program memory requirements Appendix B shows a slightly different implementation (only the EVAL_Y MACRO is different) that optimizes program memory usage over speed Table shows the time and resources required to implement different size PLAs DS00511E-page AN511 FIGURE 1: A SIMPLE PLA AND Plane OR Plane P23 P22 P21 P20 FIGURE 2: RB5 RB4 RB3 RB2 RB1 RB0 RC0 RC1 RC2 RC3 RC4 RC5 RC6 A5 A4 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 RC7 RB6 A6 Y7 RB7 A7 • • • • • • • • P3 P2 P1 P0 BINARY TO 7-SEGMENT CONVERSION EXAMPLE SEG0 A3 SEG1 A2 SEG2 BINARY INPUT A1 SEG3 7-SEG OUTPUT A0 LSB SEG4 SEG5 SEG6 BINARY 7-SEGMENT CONVERTER (COMMON CATHODE) Truth Table: DS00511E-page Product Terms HEX A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 0 0 1 1 1 1 1 1 1 0 0 1 P1 P2 P3 0 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 P4 P5 P6 P7 P8 P9 A B C 1 0 1 0 1 1 0 0 1 1 1 1 1 P10 P11 P12 D E 1 1 1 0 1 1 1 1 1 P13 P14 F 1 1 0 1 P15 = A3, A2, A1, A0 P0 = A3, A2, A1, A0 1997 Microchip Technology Inc AN511 SPEED/RESPONSE TIME EXAMPLE 1: The worst case response time of a PLA implemented in this fashion can be calculated as follows First, we define TD = time required to execute the PLA program assuming the worst case program branches are taken Then the maximum propagation delay time from input change to valid output = 2TD This is because if an input changes just after the program reads the input port, its effect will not show up until the program completes the current execution cycle, re-reads the input and recalculates the output This is shown in Figure There are ways to improve the delay time, such as sample inputs several times throughout the PLA program and if an input change is sensed, return to the beginning rather than execute the rest of the evaluation code begin pla 88 op_tbl If the number of inputs is small (8 or less) then a simple table lookup method can be used to implement the PLA This will improve execution time to around µs (@ MHz input clock) The following code implements the Binary Coded Decimal (BCD) to 7-segment conversion (Figure 2) using this technique Number of Products 8 24 8 48 16 16 64 20 24 80 NI = Number of inputs NIW NP = = NI Number of input words, NIW = Number of products NPW = NO = NOW = 0ffh ; ;Port_b = input ; ;Port_c = output Port_b,w ;Read input 0fh ;Mask off bits 7:4 op_tbl ; Port_c ;Write output pla88 ; pc ;Computed jump for ;table lookup b”00111111”; b”00000110”; b”01011011”; b”01001111”; b”01100110”; b”01101101”; b”01111101”; b”00000111”; b”01111111”; b”01100111”; b”01110111”; b”01111000”; b”00111001”; b”01011110”; b”01111001”; b”01110001”; EXECUTION TIME AND RESOURCES NECESSARY FOR DIFFERENT SIZE PLAS Number of Number of Inputs Outputs Including Including FDBK FDBK and O/E Control If movlw tris clrw tris movf andlw call movwf goto addwf retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw A Table Lookup Method for Small PLA Implementation TABLE 1: LOOKUP TABLE – PLA METHOHD N Number of product words, i.e NPW = P Number of output words N Number of output words, i.e., NOW = O 1997 Microchip Technology Inc Number of RAM Locations Required NRAM Number of Memory Locations Required NROM Number of Instruction Cycles to Execute PLA NCYC Real-time @ 20 MHz to Execute PLA 228 228 45.6 µs Time Efficient 10 222 352 70.4 µs Code Efficient 447 447 89.8 µs Time Efficient 13 384 535 107 µs Code Efficient 12 1042 1042 208.4 µs Time Efficient 22 843 1250 250 µs Code Efficient 16 1661 1661 372.2 µs Time Efficient 40 1462 2221 444.2 µs Code Efficient Then, NRAM @ NIW + NPW : Time Efficient NRAM @ NIW + NOW + NPW + 2: Code Efficient NROM @ + NPW + NOW + NP [2 + 3NIW] + No • 4: Time Efficient NROM @ 17 + NPW + NOW + NP [2 + 3NIW] + No [NPW + 3]: Code Efficient NCYC @ + NPW + NOW + NP[2 + 3NIW] + No [2NPW • 4]: Time Efficient NCYC @ + NPW + NOW + NP [2 + 3NIW] + 5N [NPW + 1]: Code Efficient DS00511E-page AN511 FIGURE 3: PLA PROGRAM FLOW Read Inputs Read Inputs TD1 Evaulate Product Terms No TD Has Input Changed? Yes Evaulate Output Terms Evaluate Product Terms TD2 TD Write to Output Ports Yes A very simple PLA evaluation flow Has Input Changed? No Input_a Evaluate Output Terms TD3 Input_b Write Output to Ports Output_x TD TD New valid Output TPROP ≈ 2TD In this simple implementation, the maximum propagation delay from input change to output change is ≈ 2TD FIGURE 4: Inputs A0 A1 An • • • Combinational Logic • • • • • • F0 F1 • • • Fp DS00511E-page • • • Ym In this example TD < TPROP < TD + TD3 IMPLEMENTING AN ASYNCHRONOUS STATE MACHINE ASYNCHRONOUS STATE MACHINE Y0 Y1 More complex program flow can be used, such as this one to reduce TPROP Outputs The concept can be easily extended to implement sequential logic (i.e., a state machine) Figure shows a state machine with n inputs (A0:An), m outputs (Y0:Ym) and p states that feedback as inputs to the PLA (F0:Fp) In a PIC16C5X the states will be stored as bits in RAM location Input will now mean input from a port as well as from the feedback registers Figure shows an example PLA with eight inputs A0,A1, ,A7 that are connected to PORTB pins RB0,RB1, ,RB7 This example PLA has a total of 24 outputs of which eight are actual outputs, another eight are output enable control for the outputs and the other eight are feedbacks (or states) The PLA shown here, therefore, in essence implements an asynchronous state machine (i.e., there is no system clock) 1997 Microchip Technology Inc AN511 FIGURE 5: EXAMPLE OF A LARGER PLA IMPLEMENTATION A0 RB0 A1 RB1 A2 RB2 A3 RB3 A4 RB4 A5 RB5 A6 RB6 A7 RB7 F0 F1 F2 F3 F4 F5 F6 F7 RC1 Y2 RC2 Y3 RC3 Y4 RC4 Y5 RC5 Y6 RC6 Y7 RC7 P63 P62 P61 RC0 Y1 • • • • • • • • • Y0 P3 P2 P1 P0 Internal RAM Locations OR7 OR6 OR5 OR4 OR3 OR2 OR1 OR0 TRIS register for PORTC This example shows 16 inputs (including feedback), 64 product terms and 24 outputs including feedback and O/E control This example demonstrates that O/E control is easily implementable using PIC16C5X’s bi-directional ports with Tri-State control Tri-State is a registered trademark of National Semiconductor Corporation 1997 Microchip Technology Inc DS00511E-page-5 AN511 FIGURE 6: SYNCHRONOUS STATE MACHINE IMPLEMENTATION A0 Y0 Yes Clock = 1? Ai Combinational Logic F0s Q D Q D No Evaluate PLA outputs F0m Output Y0 - Yi F1m Output F0m - Fpm Fpm Clock = 0? CK F1s Yi CK Fps Q Yes D CK CLOCK No Fmaster → Fslave Flowchart for implementing synchronous state machine Clock is input to an I/O port Fmaster and Fslave are RAM locations that store state variables F0m, Fpm and F0s, Fps respectively Clock A0:Ai F0s:Fps F0m:Fpm Y0:Yi IMPLEMENTING A SYNCHRONOUS STATE MACHINE In a synchronous system (Figure 6) usually all inputs are stable at the falling (or rising) edge of the system clock The state machine samples inputs on the falling edge, then evaluates state and output information The state outputs are latched by the rising edge of the clock before feeding them back to the input (so that they are stable at the falling edge of the clock) To implement such a state machine, the system clock will have to be polled by an input pin When a falling edge is detected, the PLA evaluation procedure will be invoked to compute outputs and write them to output pins The PLA procedure will also determine the new state variables, F0m, F1m, ,Fpm and store them in RAM The program will then wait until a rising edge on the clock input is detected and copy the “master” state variables (F0m, ,Fpm) to slave state variables (F0s,F1s, ,Fps) This step emulates the feedback flip-flops DS00511E-page SUMMARY In conclusion, the PIC16C5X can implement a generic PLA equation and provide a quick, low cost solution where system operation speed is not critical 1997 Microchip Technology Inc AN511 Please check the Microchip BBS for the latest version of the source code Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required) APPENDIX A: PLA IMPLEMENTATION: TIME EFFICIENT APPROACH MPASM 01.40 Released LOC OBJECT CODE VALUE 0000000C 0000000D 0000000E 0000000F 00000010 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000003 00000006 00000007 00000000 0000000F 00000001 0000000F 00000002 PLA1A.ASM 1-16-1997 12:28:25 PAGE LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 00052 00053 00054 1997 Microchip Technology Inc LIST P = 16C54, n = 66 ; ;******************************************************************* ; pla1a.asm : ; This procedure implements a simple AND-OR PLA with: ; ; inputs := A7 A6 A5 A4 A3 A2 A1 A0 ; 24 product terms := P23 P22 P0 ; outputs := Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 ; ; The eight inputs are assumed to be connected to PORT RB such that ; RB0 = A0, RB1 = A1, , RB7 = A7 ; The outputs are programmed to appear on port RC such that ; RC0 = Y0, RC1 = Y1, , RC7 = Y7 ; ; This implementation optimizes both speed & program memory usage ; ; Program: PLA1A.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;******************************************************************** ; ; define RAM locations used: ; input equ d’12’ ; RAM location 12 holds input Y_reg equ d’13’ ; holds output result Preg_a Preg_b Preg_c equ equ equ d’14’ d’15’ d’16’ ; Product terms P0 to P7 Preg_a = P0 ; Product terms P8 to P15 Preg_b = P8 ; Product terms P16 to P23 Preg_c = P16 ; define some constants and file addresses: ; bit0 equ ; bit1 equ ; bit2 equ ; bit3 equ ; bit4 equ ; bit5 equ ; bit6 equ ; bit7 equ ; ; status equ ; port_b equ ; port_c equ ; ; ; define the AND plane programming variables: ; P0_x equ b’00000000’ ; P0_a equ b’00001111’ ; P1_x equ b’00000001’ ; P1_a equ b’00001111’ ; P2_x equ b’00000010’ ; DS00511E-page-7 AN511 0000000F 00000003 0000000F 00000004 0000000F 00000005 0000000F 00000006 0000000F 00000007 0000000F 00000008 0000000F 00000009 0000000F 0000000A 0000000F 0000000B 0000000F 0000000C 0000000F 0000000D 0000000F 0000000E 0000000F 0000000F 0000000F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000000ED 000000D7 00000000 0000009F 00000027 00000000 000000FB 0000002F 00000000 0000006D 00000079 00000000 00000045 000000FD 00000000 00000071 000000DF 00000000 0000007C 000000EF DS00511E-page 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 P2_a P3_x P3_a P4_x P4_a P5_x P5_a P6_x P6_a P7_x P7_a P8_x P8_a P9_x P9_a P10_x P10_a P11_x P11_a P12_x P12_a P13_x P13_a P14_x P14_a P15_x P15_a P16_x P16_a P17_x P17_a P18_x P18_a P19_x P19_a P20_x P20_a P21_x P21_a P22_x P22_a P23_x P23_a equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ b’00001111’ b’00000011’ b’00001111’ b’00000100’ b’00001111’ b’00000101’ b’00001111’ b’00000110’ b’00001111’ b’00000111’ b’00001111’ b’00001000’ b’00001111’ b’00001001’ b’00001111’ b’00001010’ b’00001111’ b’00001011’ b’00001111’ b’00001100’ b’00001111’ b’00001101’ b’00001111’ b’00001110’ b’00001111’ b’00001111’ b’00001111’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; define OR plane programming variables: OR_a0 OR_b0 OR_c0 OR_a1 OR_b1 OR_c1 OR_a2 OR_b2 OR_c2 OR_a3 OR_b3 OR_c3 OR_a4 OR_b4 OR_c4 OR_a5 OR_b5 OR_c5 OR_a6 OR_b6 equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ b’11101101’ b’11010111’ b’00000000’ b’10011111’ b’00100111’ b’00000000’ b’11111011’ b’00101111’ b’00000000’ b’01101101’ b’01111001’ b’00000000’ b’01000101’ b’11111101’ b’00000000’ b’01110001’ b’11011111’ b’00000000’ b’01111100’ b’11101111’ ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; for output Y0 for output Y1 for output Y2 for output Y3 for output Y4 for output Y5 for output Y6 1997 Microchip Technology Inc AN511 00000000 00000000 00000000 00000000 01FF 01FF 0A00 0000 0000 0902 0001 0A00 0002 0003 0004 0005 0006 0007 0008 0009 0CFF 0006 0206 002C 006E 006F 0070 006D 000A 000B 000C 000D 000E 020C 0F00 0E0F 0643 050E 000F 020C 0010 0F01 0011 0E0F 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 M M M M M 00178 M M M 1997 Microchip Technology Inc OR_c6 OR_a7 OR_b7 OR_c7 equ equ equ equ b’00000000’ b’00000000’ b’00000000’ b’00000000’ begin org 01ffh goto main ; ; for output Y7 ; ; ; ; org 000h ; ; define macro to evaluate product (AND) term: ; main call pla88 ; goto main ; ; EVAL_P MACRO Preg_x,bit_n,Pn_x,Pn_a movf input,W xorlw Pn_x andlw Pn_a btfsc status,bit2 bsf Preg_x,bit_n ENDM ; ; ; ; skip if zero bit not set ; product term = ; define macro to load OR term constants: ; EVAL_Y MACRO OR_an,OR_bn,OR_cn,bit_n LOCAL SETBIT ; movf Preg_a,W ; andlw OR_an ; btfss status,bit2 ; goto SETBIT ; SETBIT movf andlw btfss goto Preg_b,W OR_bn ; status,bit2 SETBIT ; ; movf andlw btfss Preg_c,W OR_cn ; status,bit2 Y_reg,bit_n ; bsf ; ; ; ENDM ; now the PLA evaluation procedure: ; pla88 movlw 0ffh tris movf port_b,W movwf input clrf Preg_a clrf Preg_b clrf Preg_c clrf Y_reg and_pl EVAL_P ; ; ; ; ; ; ; ; port_b = input read input store input in a register clear Product register a clear Product register b clear Product register c clear output register Preg_a,bit0,P0_x,P0_a movf input,W ; xorlw P0_x ; andlw P0_a ; btfsc status,bit2 ; skip if zero bit not set bsf Preg_a,bit0 ; product term = EVAL_P Preg_a,bit1,P1_x,P1_a movf input,W ; xorlw P1_x ; andlw P1_a ; DS00511E-page-9 AN511 0012 0643 0013 052E 0014 0015 0016 0017 0018 020C 0F02 0E0F 0643 054E 0019 001A 001B 001C 001D 020C 0F03 0E0F 0643 056E 001E 001F 0020 0021 0022 020C 0F04 0E0F 0643 058E 0023 0024 0025 0026 0027 020C 0F05 0E0F 0643 05AE 0028 0029 002A 002B 002C 020C 0F06 0E0F 0643 05CE 002D 002E 002F 0030 0031 020C 0F07 0E0F 0643 05EE 0032 0033 0034 0035 0036 020C 0F08 0E0F 0643 050F 0037 0038 0039 003A 003B 020C 0F09 0E0F 0643 052F 003C 003D 003E 003F 0040 020C 0F0A 0E0F 0643 054F 0041 0042 0043 0044 0045 020C 0F0B 0E0F 0643 056F 0046 020C 0047 0F0C DS00511E-page 10 M M 00179 M M M M M 00180 M M M M M 00181 M M M M M 00182 M M M M M 00183 M M M M M 00184 M M M M M 00185 00186 M M M M M 00187 M M M M M 00188 M M M M M 00189 M M M M M 00190 M M btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf status,bit2 ; skip if Preg_a,bit1 ; product Preg_a,bit2,P2_x,P2_a input,W ; P2_x ; P2_a ; status,bit2 ; skip if Preg_a,bit2 ; product Preg_a,bit3,P3_x,P3_a input,W ; P3_x ; P3_a ; status,bit2 ; skip if Preg_a,bit3 ; product Preg_a,bit4,P4_x,P4_a input,W ; P4_x ; P4_a ; status,bit2 ; skip if Preg_a,bit4 ; product Preg_a,bit5,P5_x,P5_a input,W ; P5_x ; P5_a ; status,bit2 ; skip if Preg_a,bit5 ; product Preg_a,bit6,P6_x,P6_a input,W ; P6_x ; P6_a ; status,bit2 ; skip if Preg_a,bit6 ; product Preg_a,bit7,P7_x,P7_a input,W ; P7_x ; P7_a ; status,bit2 ; skip if Preg_a,bit7 ; product EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw Preg_b,bit0,P8_x,P8_a input,W ; P8_x ; P8_a ; status,bit2 ; skip if Preg_b,bit0 ; product Preg_b,bit1,P9_x,P9_a input,W ; P9_x ; P9_a ; status,bit2 ; skip if Preg_b,bit1 ; product Preg_b,bit2,P10_x,P10_a input,W ; P10_x ; P10_a ; status,bit2 ; skip if Preg_b,bit2 ; product Preg_b,bit3,P11_x,P11_a input,W ; P11_x ; P11_a ; status,bit2 ; skip if Preg_b,bit3 ; product Preg_b,bit4,P12_x,P12_a input,W ; P12_x ; zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = 1997 Microchip Technology Inc AN511 0048 0E0F 0049 0643 004A 058F 004B 004C 004D 004E 004F 020C 0F0D 0E0F 0643 05AF 0050 0051 0052 0053 0054 020C 0F0E 0E0F 0643 05CF 0055 0056 0057 0058 0059 020C 0F0F 0E0F 0643 05EF 005A 005B 005C 005D 005E 020C 0F00 0E00 0643 0510 005F 0060 0061 0062 0063 020C 0F00 0E00 0643 0530 0064 0065 0066 0067 0068 020C 0F00 0E00 0643 0550 0069 006A 006B 006C 006D 020C 0F00 0E00 0643 0570 006E 006F 0070 0071 0072 020C 0F00 0E00 0643 0590 0073 0074 0075 0076 0077 020C 0F00 0E00 0643 05B0 0078 0079 007A 007B 007C 020C 0F00 0E00 0643 05D0 007D 020C M M M 00191 M M M M M 00192 M M M M M 00193 M M M M M 00194 00195 M M M M M 00196 M M M M M 00197 M M M M M 00198 M M M M M 00199 M M M M M 00200 M M M M M 00201 M M M M M 00202 M 1997 Microchip Technology Inc andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf P12_a ; status,bit2 ; skip if Preg_b,bit4 ; product Preg_b,bit5,P13_x,P13_a input,W ; P13_x ; P13_a ; status,bit2 ; skip if Preg_b,bit5 ; product Preg_b,bit6,P14_x,P14_a input,W ; P14_x ; P14_a ; status,bit2 ; skip if Preg_b,bit6 ; product Preg_b,bit7,P15_x,P15_a input,W ; P15_x ; P15_a ; status,bit2 ; skip if Preg_b,bit7 ; product EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf Preg_c,bit0,P16_x,P16_a input,W ; P16_x ; P16_a ; status,bit2 ; skip if Preg_c,bit0 ; product Preg_c,bit1,P17_x,P17_a input,W ; P17_x ; P17_a ; status,bit2 ; skip if Preg_c,bit1 ; product Preg_c,bit2,P18_x,P18_a input,W ; P18_x ; P18_a ; status,bit2 ; skip if Preg_c,bit2 ; product Preg_c,bit3,P19_x,P19_a input,W ; P19_x ; P19_a ; status,bit2 ; skip if Preg_c,bit3 ; product Preg_c,bit4,P20_x,P20_a input,W ; P20_x ; P20_a ; status,bit2 ; skip if Preg_c,bit4 ; product Preg_c,bit5,P21_x,P21_a input,W ; P21_x ; P21_a ; status,bit2 ; skip if Preg_c,bit5 ; product Preg_c,bit6,P22_x,P22_a input,W ; P22_x ; P22_a ; status,bit2 ; skip if Preg_c,bit6 ; product Preg_c,bit7,P23_x,P23_a input,W ; zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = DS00511E-page-11 AN511 007E 007F 0080 0081 0F00 0E00 0643 05F0 0000 0082 020E 0083 0EED 0084 0743 0085 0A8D 0086 0087 0088 0089 020F 0ED7 0743 0A8D 008A 008B 008C 008D 0210 0E00 0743 050D 0000 008E 020E 008F 0E9F 0090 0743 0091 0A99 0092 0093 0094 0095 020F 0E27 0743 0A99 0096 0097 0098 0099 0210 0E00 0743 052D 0000 009A 020E 009B 0EFB 009C 0743 009D 0AA5 009E 009F 00A0 00A1 020F 0E2F 0743 0AA5 00A2 00A3 00A4 00A5 0210 0E00 0743 054D 0000 00A6 020E 00A7 0E6D 00A8 0743 00A9 0AB1 00AA 00AB 00AC 00AD 020F 0E79 0743 0AB1 00AE 0210 DS00511E-page 12 M M M M 00203 00204 M M M M M M M M M M M M M M M 00205 M M M M M M M M M M M M M M M 00206 M M M M M M M M M M M M M M M 00207 M M M M M M M M M M M M or_pl SETBIT SETBIT SETBIT xorlw andlw btfsc bsf P23_x P23_a status,bit2 Preg_c,bit7 ; ; ; skip if zero bit not set ; product term = EVAL_Y LOCAL movf andlw btfss goto OR_a0,OR_b0,OR_c0,bit0 SETBIT ; Preg_a,W ; OR_a0 ; status,bit2 ; SETBIT ; movf andlw btfss goto Preg_b,W OR_b0 ; status,bit2 SETBIT movf andlw btfss bsf EVAL_Y LOCAL movf andlw btfss goto Preg_c,W ; OR_c0 ; status,bit2 ; Y_reg,bit0 ; OR_a1,OR_b1,OR_c1,bit1 SETBIT ; Preg_a,W ; OR_a1 ; status,bit2 ; SETBIT ; movf andlw btfss goto Preg_b,W OR_b1 status,bit2 SETBIT movf andlw btfss bsf EVAL_Y LOCAL movf andlw btfss goto Preg_c,W ; OR_c1 ; status,bit2 ; Y_reg,bit1 ; OR_a2,OR_b2,OR_c2,bit2 SETBIT ; Preg_a,W ; OR_a2 ; status,bit2 ; SETBIT ; movf andlw btfss goto Preg_b,W OR_b2 status,bit2 SETBIT ; movf andlw btfss bsf EVAL_Y LOCAL movf andlw btfss goto Preg_c,W ; OR_c2 ; status,bit2 ; Y_reg,bit2 ; OR_a3,OR_b3,OR_c3,bit3 SETBIT ; Preg_a,W ; OR_a3 ; status,bit2 ; SETBIT ; movf andlw btfss goto Preg_b,W OR_b3 status,bit2 SETBIT ; ; ; ; movf Preg_c,W ; ; ; ; ; ; ; ; ; ; ; 1997 Microchip Technology Inc AN511 00AF 0E00 00B0 0743 00B1 056D 0000 00B2 020E 00B3 0E45 00B4 0743 00B5 0ABD 00B6 00B7 00B8 00B9 020F 0EFD 0743 0ABD 00BA 00BB 00BC 00BD 0210 0E00 0743 058D 0000 00BE 020E 00BF 0E71 00C0 0743 00C1 0AC9 Preg_b,W 00C3 0EDF 00C4 0743 00C5 0AC9 00C6 00C7 00C8 00C9 0210 0E00 0743 05AD 0000 00CA 020E 00CB 0E7C 00CC 0743 00CD 0AD5 00CE 00CF 00D0 00D1 020F 0EEF 0743 0AD5 00D2 00D3 00D4 00D5 0210 0E00 0743 05CD 0000 00D6 020E 00D7 0E00 00D8 0743 00D9 0AE1 00DA 00DB 00DC 00DD 020F 0E00 0743 0AE1 00DE 0210 00DF 0E00 00E0 0743 M M M SETBIT 00208 M M M M M M M M M M M M M M M SETBIT 00209 M M M M M M andlw btfss bsf EVAL_Y LOCAL movf andlw btfss goto OR_c3 ; status,bit2 ; Y_reg,bit3 ; OR_a4,OR_b4,OR_c4,bit4 SETBIT ; Preg_a,W ; OR_a4 ; status,bit2 ; SETBIT ; movf andlw btfss goto Preg_b,W OR_b4 status,bit2 SETBIT movf andlw btfss bsf EVAL_Y LOCAL movf andlw btfss goto Preg_c,W ; OR_c4 ; status,bit2 ; Y_reg,bit4 ; OR_a5,OR_b5,OR_c5,bit5 SETBIT ; Preg_a,W ; OR_a5 ; status,bit2 ; SETBIT ; M M M M M M M M SETBIT 00210 M M M M M M M M M M M M M M M SETBIT 00211 M M M M M M M M M M M M M M andlw btfss goto OR_b5 status,bit2 SETBIT movf andlw btfss bsf EVAL_Y LOCAL movf andlw btfss goto Preg_c,W ; OR_c5 ; status,bit2 ; Y_reg,bit5 ; OR_a6,OR_b6,OR_c6,bit6 SETBIT ; Preg_a,W ; OR_a6 ; status,bit2 ; SETBIT ; movf andlw btfss goto Preg_b,W OR_b6 status,bit2 SETBIT movf andlw btfss EVAL_Y LOCAL movf andlw btfss goto Preg_c,W ; OR_c6 ; status,bit2 ; Y_reg,bit6 ; OR_a7,OR_b7,OR_c7,bit7 SETBIT ; Preg_a,W ; OR_a7 ; status,bit2 ; SETBIT ; movf andlw btfss goto Preg_b,W OR_b7 status,bit2 SETBIT ; ; ; ; movf andlw btfss Preg_c,W OR_c7 status,bit2 ; ; ; ; ; ; ; ; 1997 Microchip Technology Inc bsf ; ; ; ; ; ; ; DS00511E-page-13 AN511 00E1 05ED 00E2 00E3 00E4 00E5 00E6 0040 0007 020D 0027 0800 00E7 0000 M 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 SETBIT : : : : : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX Y_reg,bit7 ; Y_reg now contains output values: wr_out clrw tris movf Y_reg,W movwf port_c retlw ZZZ ; ; ; port_c = output ; ; Y_reg -> port_c ; nop END MEMORY USAGE MAP (‘X’ = Used, 0000 0040 0080 00C0 01C0 bsf ‘-’ = Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXX - XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX X All other memory blocks unused Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : DS00511E-page 14 0 reported, reported, 233 279 suppressed suppressed 1997 Microchip Technology Inc AN511 Please check the Microchip BBS for the latest version of the source code Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required) APPENDIX B: PLA IMPLEMENTATION: CODE EFFICIENT APPROACH MPASM 01.40 Released LOC OBJECT CODE VALUE 0000000C 0000000D 0000000E 0000000F 00000010 00000012 00000013 00000014 00000015 00000016 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000003 00000006 00000007 PLA1B.ASM 1-16-1997 12:29:06 PAGE LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 00052 00053 00054 00055 1997 Microchip Technology Inc LIST P = 16C54, n = 66 ; ;******************************************************************* ; pla1b.asm : ; This procedure implements a simple AND-OR PLA with: ; ; inputs := A7 A6 A5 A4 A3 A2 A1 A0 ; 24 product terms := P23 P22 P0 ; outputs := Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 ; ; The eight inputs are assumed to be connected to PORT RB such that ; RB0 = A0, RB1 = A1, , RB7 = A7 ; The outputs are programmed to appear on port RC such that ; RC0 = Y0, RC1 = Y1, , RC7 = Y7 ; ; This implementation optimizes program memory usage over ; speed ; ; Program: PLA1B.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;******************************************************************* ; ; define RAM locations used: ; input equ d’12’ ; RAM location 12 holds input Y_reg equ d’13’ ; holds output result Preg_a Preg_b Preg_c equ equ equ d’14’ d’15’ d’16’ ; Product terms P0 to P7 Preg_a = P0 ; Product terms P8 to P15 Preg_b = P8 ; Product terms P16 to P23 Preg_c = P16 Pn_x Pn_a OR_a OR_b OR_c equ equ equ equ equ d’18’ d’19’ d’20’ d’21’ d’22’ ; ; ; ; ; ; define some constants and file addresses: ; bit0 equ ; bit1 equ ; bit2 equ ; bit3 equ ; bit4 equ ; bit5 equ ; bit6 equ ; bit7 equ ; ; status equ ; port_b equ ; port_c equ ; ; ; define the AND plane programming variables: DS00511E-page-15 AN511 00000000 0000000F 00000001 0000000F 00000002 0000000F 00000003 0000000F 00000004 0000000F 00000005 0000000F 00000006 0000000F 00000007 0000000F 00000008 0000000F 00000009 0000000F 0000000A 0000000F 0000000B 0000000F 0000000C 0000000F 0000000D 0000000F 0000000E 0000000F 0000000F 0000000F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000000ED 000000D7 00000000 0000009F 00000027 00000000 000000FB 0000002F 00000000 0000006D 00000079 00000000 00000045 000000FD DS00511E-page 16 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 ; P0_x P0_a P1_x P1_a P2_x P2_a P3_x P3_a P4_x P4_a P5_x P5_a P6_x P6_a P7_x P7_a P8_x P8_a P9_x P9_a P10_x P10_a P11_x P11_a P12_x P12_a P13_x P13_a P14_x P14_a P15_x P15_a P16_x P16_a P17_x P17_a P18_x P18_a P19_x P19_a P20_x P20_a P21_x P21_a P22_x P22_a P23_x P23_a equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ b’00000000’ b’00001111’ b’00000001’ b’00001111’ b’00000010’ b’00001111’ b’00000011’ b’00001111’ b’00000100’ b’00001111’ b’00000101’ b’00001111’ b’00000110’ b’00001111’ b’00000111’ b’00001111’ b’00001000’ b’00001111’ b’00001001’ b’00001111’ b’00001010’ b’00001111’ b’00001011’ b’00001111’ b’00001100’ b’00001111’ b’00001101’ b’00001111’ b’00001110’ b’00001111’ b’00001111’ b’00001111’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; define OR plane programming variables: OR_a0 OR_b0 OR_c0 OR_a1 OR_b1 OR_c1 OR_a2 OR_b2 OR_c2 OR_a3 OR_b3 OR_c3 OR_a4 OR_b4 equ equ equ equ equ equ equ equ equ equ equ equ equ equ b’11101101’ b’11010111’ b’00000000’ b’10011111’ b’00100111’ b’00000000’ b’11111011’ b’00101111’ b’00000000’ b’01101101’ b’01111001’ b’00000000’ b’01000101’ b’11111101’ ; ; ; ; ; ; ; ; ; ; ; ; ; ; for output Y0 for output Y1 for output Y2 for output Y3 for output Y4 1997 Microchip Technology Inc AN511 00000000 00000071 000000DF 00000000 0000007C 000000EF 00000000 00000000 00000000 00000000 01FF 01FF 0A00 0000 0000 090B 0001 0A00 0002 020E 0003 0174 0004 020F 0005 0175 0006 0210 0007 0156 0008 0114 0009 0115 000A 0800 000B 000C 000D 000E 0CFF 0006 0206 002C 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 1997 Microchip Technology Inc OR_c4 OR_a5 OR_b5 OR_c5 OR_a6 OR_b6 OR_c6 OR_a7 OR_b7 OR_c7 equ equ equ equ equ equ equ equ equ equ b’00000000’ b’01110001’ b’11011111’ b’00000000’ b’01111100’ b’11101111’ b’00000000’ b’00000000’ b’00000000’ b’00000000’ ; ; for output Y5 ; ; ; for output Y6 ; ; ; for output Y7 ; ; begin goto org main ; ; 01ffh org 000h ; ; define macro to evaluate product (AND) term: ; main call pla88 ; goto main ; ; EVAL_P MACRO Preg_x,bit_n,Pn_x,Pn_a movf input,W xorlw Pn_x andlw Pn_a btfsc status,bit2 bsf Preg_x,bit_n ENDM ; ; ; ; skip if zero bit not set ; product term = ; define macro to load OR term constants: ; EVAL_Y MACRO OR_an,OR_bn,OR_cn,bit_n movlw OR_an ; load constants movwf OR_a ; movlw OR_bn ; movwf OR_b ; movlw OR_cn ; movwf OR_c ; call EVAL1 ; btfss status,bit2 ; bsf Y_reg,bit_n ; ENDM ; define procedure to evaluate output (OR) term: ; EVAL1 movf Preg_a,W ; andwf OR_a,1 ; movf andwf Preg_b,W OR_b,1 ; ; movf andwf Preg_c,W OR_c,W ; ; iorwf iorwf retlw OR_a,W OR_b,W ; ; ; ; now the PLA evaluation procedure: ; pla88 movlw 0ffh tris movf port_b,W movwf input W = implies Yn = ; ; port_b = input ; read input ; store input in a register DS00511E-page-17 AN511 000F 0010 0011 0012 006E 006F 0070 006D 0013 0014 0015 0016 0017 020C 0F00 0E0F 0643 050E 0018 0019 001A 001B 001C 020C 0F01 0E0F 0643 052E 001D 001E 001F 0020 0021 020C 0F02 0E0F 0643 054E 0022 0023 0024 0025 0026 020C 0F03 0E0F 0643 056E 0027 0028 0029 002A 002B 020C 0F04 0E0F 0643 058E 002C 002D 002E 002F 0030 020C 0F05 0E0F 0643 05AE 0031 0032 0033 0034 0035 020C 0F06 0E0F 0643 05CE 0036 0037 0038 0039 003A 020C 0F07 0E0F 0643 05EE 003B 003C 003D 003E 003F 020C 0F08 0E0F 0643 050F 0040 0041 0042 0043 0044 020C 0F09 0E0F 0643 052F DS00511E-page 18 00188 00189 00190 00191 00192 00193 and_pl M M M M M 00194 M M M M M 00195 M M M M M 00196 M M M M M 00197 M M M M M 00198 M M M M M 00199 M M M M M 00200 M M M M M 00201 00202 M M M M M 00203 M M M M M clrf clrf clrf clrf EVAL_P Preg_a Preg_b Preg_c Y_reg ; ; ; ; clear clear clear clear Product register a Product register b Product register c output register Preg_a,bit0,P0_x,P0_a movf input,W ; xorlw P0_x ; andlw P0_a ; btfsc status,bit2 ; skip if bsf Preg_a,bit0 ; product EVAL_P Preg_a,bit1,P1_x,P1_a movf input,W ; xorlw P1_x ; andlw P1_a ; btfsc status,bit2 ; skip if bsf Preg_a,bit1 ; product EVAL_P Preg_a,bit2,P2_x,P2_a movf input,W ; xorlw P2_x ; andlw P2_a ; btfsc status,bit2 ; skip if bsf Preg_a,bit2 ; product EVAL_P Preg_a,bit3,P3_x,P3_a movf input,W ; xorlw P3_x ; andlw P3_a ; btfsc status,bit2 ; skip if bsf Preg_a,bit3 ; product EVAL_P Preg_a,bit4,P4_x,P4_a movf input,W ; xorlw P4_x ; andlw P4_a ; btfsc status,bit2 ; skip if bsf Preg_a,bit4 ; product EVAL_P Preg_a,bit5,P5_x,P5_a movf input,W ; xorlw P5_x ; andlw P5_a ; btfsc status,bit2 ; skip if bsf Preg_a,bit5 ; product EVAL_P Preg_a,bit6,P6_x,P6_a movf input,W ; xorlw P6_x ; andlw P6_a ; btfsc status,bit2 ; skip if bsf Preg_a,bit6 ; product EVAL_P Preg_a,bit7,P7_x,P7_a movf input,W ; xorlw P7_x ; andlw P7_a ; btfsc status,bit2 ; skip if bsf Preg_a,bit7 ; product EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf Preg_b,bit0,P8_x,P8_a input,W ; P8_x ; P8_a ; status,bit2 ; skip if Preg_b,bit0 ; product Preg_b,bit1,P9_x,P9_a input,W ; P9_x ; P9_a ; status,bit2 ; skip if Preg_b,bit1 ; product zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = 1997 Microchip Technology Inc AN511 0045 0046 0047 0048 0049 020C 0F0A 0E0F 0643 054F 004A 004B 004C 004D 004E 020C 0F0B 0E0F 0643 056F 004F 0050 0051 0052 0053 020C 0F0C 0E0F 0643 058F 0054 0055 0056 0057 0058 020C 0F0D 0E0F 0643 05AF 0059 005A 005B 005C 005D 020C 0F0E 0E0F 0643 05CF 005E 005F 0060 0061 0062 020C 0F0F 0E0F 0643 05EF 0063 0064 0065 0066 0067 020C 0F00 0E00 0643 0510 0068 0069 006A 006B 006C 020C 0F00 0E00 0643 0530 006D 006E 006F 0070 0071 020C 0F00 0E00 0643 0550 0072 0073 0074 0075 0076 020C 0F00 0E00 0643 0570 0077 0078 0079 007A 020C 0F00 0E00 0643 00204 M M M M M 00205 M M M M M 00206 M M M M M 00207 M M M M M 00208 M M M M M 00209 M M M M M 00210 00211 M M M M M 00212 M M M M M 00213 M M M M M 00214 M M M M M 00215 M M M M 1997 Microchip Technology Inc EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf Preg_b,bit2,P10_x,P10_a input,W ; P10_x ; P10_a ; status,bit2 ; skip if Preg_b,bit2 ; product Preg_b,bit3,P11_x,P11_a input,W ; P11_x ; P11_a ; status,bit2 ; skip if Preg_b,bit3 ; product Preg_b,bit4,P12_x,P12_a input,W ; P12_x ; P12_a ; status,bit2 ; skip if Preg_b,bit4 ; product Preg_b,bit5,P13_x,P13_a input,W ; P13_x ; P13_a ; status,bit2 ; skip if Preg_b,bit5 ; product Preg_b,bit6,P14_x,P14_a input,W ; P14_x ; P14_a ; status,bit2 ; skip if Preg_b,bit6 ; product Preg_b,bit7,P15_x,P15_a input,W ; P15_x ; P15_a ; status,bit2 ; skip if Preg_b,bit7 ; product EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc Preg_c,bit0,P16_x,P16_a input,W ; P16_x ; P16_a ; status,bit2 ; skip if Preg_c,bit0 ; product Preg_c,bit1,P17_x,P17_a input,W ; P17_x ; P17_a ; status,bit2 ; skip if Preg_c,bit1 ; product Preg_c,bit2,P18_x,P18_a input,W ; P18_x ; P18_a ; status,bit2 ; skip if Preg_c,bit2 ; product Preg_c,bit3,P19_x,P19_a input,W ; P19_x ; P19_a ; status,bit2 ; skip if Preg_c,bit3 ; product Preg_c,bit4,P20_x,P20_a input,W ; P20_x ; P20_a ; status,bit2 ; skip if zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set term = zero bit not set DS00511E-page-19 AN511 007B 0590 007C 007D 007E 007F 0080 020C 0F00 0E00 0643 05B0 0081 0082 0083 0084 0085 020C 0F00 0E00 0643 05D0 0086 0087 0088 0089 008A 020C 0F00 0E00 0643 05F0 008B 008C 008D 008E 008F 0090 0091 0092 0093 0CED 0034 0CD7 0035 0C00 0036 0902 0743 050D 0094 0095 0096 0097 0098 0099 009A 009B 009C 0C9F 0034 0C27 0035 0C00 0036 0902 0743 052D 009D 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 0CFB 0034 0C2F 0035 0C00 0036 0902 0743 054D 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 0C6D 0034 0C79 0035 0C00 0036 0902 0743 056D 00AF 00B0 00B1 00B2 00B3 0C45 0034 0CFD 0035 0C00 DS00511E-page 20 M 00216 M M M M M 00217 M M M M M 00218 M M M M M 00219 00220 or_pl M M M M M M M M M 00221 M M M M M M M M M 00222 M M M M M M M M M 00223 M M M M M M M M M 00224 M M M M M bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf EVAL_P movf xorlw andlw btfsc bsf Preg_c,bit4 ; product Preg_c,bit5,P21_x,P21_a input,W ; P21_x ; P21_a ; status,bit2 ; skip if Preg_c,bit5 ; product Preg_c,bit6,P22_x,P22_a input,W ; P22_x ; P22_a ; status,bit2 ; skip if Preg_c,bit6 ; product Preg_c,bit7,P23_x,P23_a input,W ; P23_x ; P23_a ; status,bit2 ; skip if Preg_c,bit7 ; product term = EVAL_Y movlw movwf movlw movwf movlw movwf call btfss bsf EVAL_Y movlw movwf movlw movwf movlw movwf call btfss bsf EVAL_Y movlw movwf movlw movwf movlw movwf call btfss bsf EVAL_Y movlw movwf movlw movwf movlw movwf call btfss bsf EVAL_Y movlw movwf movlw movwf movlw OR_a0,OR_b0,OR_c0,bit0 OR_a0 ; load constants OR_a ; OR_b0 ; OR_b ; OR_c0 ; OR_c ; EVAL1 ; status,bit2 ; Y_reg,bit0 ; OR_a1,OR_b1,OR_c1,bit1 OR_a1 ; load constants OR_a ; OR_b1 ; OR_b ; OR_c1 ; OR_c ; EVAL1 ; status,bit2 ; Y_reg,bit1 ; OR_a2,OR_b2,OR_c2,bit2 OR_a2 ; load constants OR_a ; OR_b2 ; OR_b ; OR_c2 ; OR_c ; EVAL1 ; status,bit2 ; Y_reg,bit2 ; OR_a3,OR_b3,OR_c3,bit3 OR_a3 ; load constants OR_a ; OR_b3 ; OR_b ; OR_c3 ; OR_c ; EVAL1 ; status,bit2 ; Y_reg,bit3 ; OR_a4,OR_b4,OR_c4,bit4 OR_a4 ; load constants OR_a ; OR_b4 ; OR_b ; OR_c4 ; zero bit not set term = zero bit not set term = zero bit not set term = 1997 Microchip Technology Inc AN511 00B4 00B5 00B6 00B7 0036 0902 0743 058D 00B8 00B9 00BA 00BB 00BC 00BD 00BE 00BF 00C0 0C71 0034 0CDF 0035 0C00 0036 0902 0743 05AD 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 0C7C 0034 0CEF 0035 0C00 0036 0902 0743 05CD 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 0C00 0034 0C00 0035 0C00 0036 0902 0743 05ED 00D3 00D4 00D5 00D6 00D7 0040 0007 020D 0027 0800 00D8 0000 M movwf OR_c ; M call EVAL1 ; M btfss status,bit2 ; M bsf Y_reg,bit4 ; 00225 EVAL_Y OR_a5,OR_b5,OR_c5,bit5 M movlw OR_a5 ; load constants M movwf OR_a ; M movlw OR_b5 ; M movwf OR_b ; M movlw OR_c5 ; M movwf OR_c ; M call EVAL1 ; M btfss status,bit2 ; M bsf Y_reg,bit5 ; 00226 EVAL_Y OR_a6,OR_b6,OR_c6,bit6 M movlw OR_a6 ; load constants M movwf OR_a ; M movlw OR_b6 ; M movwf OR_b ; M movlw OR_c6 ; M movwf OR_c ; M call EVAL1 ; M btfss status,bit2 ; M bsf Y_reg,bit6 ; 00227 EVAL_Y OR_a7,OR_b7,OR_c7,bit7 M movlw OR_a7 ; load constants M movwf OR_a ; M movlw OR_b7 ; M movwf OR_b ; M movlw OR_c7 ; M movwf OR_c ; M call EVAL1 ; M btfss status,bit2 ; M bsf Y_reg,bit7 ; 00228 00229 ; Y_reg now contains output values: 00230 wr_out clrw ; 00231 tris ; port_c = output 00232 movf Y_reg,W ; 00233 movwf port_c ; Y_reg -> port_c 00234 retlw ; 00235 00236 ZZZ nop 00237 00238 END MEMORY USAGE MAP (‘X’ = Used, 0000 0040 0080 00C0 01C0 : : : : : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ‘-’ = Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX - XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX X All other memory blocks unused Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 reported, reported, 1997 Microchip Technology Inc 218 294 suppressed suppressed DS00511E-page-21 Note the following details of the code protection feature on PICmicro® MCUs • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet The person doing so may be engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as “unbreakable” Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our product If you have any further questions about this matter, please contact the local sales office nearest to you Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed, implicitly or otherwise, under any intellectual property rights Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A and other countries dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A All other trademarks mentioned herein are property of their respective companies © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved Printed on recycled paper Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® 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