electronic devices lab fet amplifier

4 Discussion of Results List of Figures Figure 1: Circuit diagram 1 Figure 3: Simulation for experiment 1 List of Tables Table 1: Comparison of circuit parameters.. ¢ Has relatively hi

INTERNATIONAL UNIVERSITY

SCHOOL OF ELECTRICAL ENGINEERING

ELECTRONIC DEVICES LAB

[FET AMPLIFIER]

Submitted by [Nguyén Phuong Khanh — EEEEIU21037]

[Phan Anh Kiét — EEEEIU21039]

Date Performed: [17/05/2023]

Lab Section: [7]

Course Instructor: [BS.MS Nguyêên Hoàng An]

Table of Contents

List of Tables

1 Theoretical Background

2 Experimental Procedure

2.1 Experiment 1

2.3 Experiment 3

3 Experimental Results

3.1 Experiment 1

3.3 Experiment 3

4 Discussion of Results

List of Figures

Figure 1: Circuit diagram 1

Figure 3: Simulation for experiment 1

List of Tables

Table 1: Comparison of circuit parameters

Table 2: Data of experiment 1

DC Voltage Source

AC Voltage Source

Reference Current

Etc

1 Theoretical Background

This lab introduces the operation of common source and common collector amplifier The main purpose of the lecture is trying to know how to build a CE, CS circuits, measure the gain and compare to the theory calculation

¢ MATERIALAND EQUIPMENT

1 Oscilloscope

2 Power Supply

3 Multimeter

4, CD4007

5 Assorted Resistors

6 Assorted Capacitors

I)_ Threshold voltage (V;)

The voltage at which the surface inversion layer just forms is called threshold voltage (Vr) The inversion layer region is a highly shallow layer, existing as a charge sheet directly below the gate AT VAT Vg exceeds the threshold voltage Vin, and the surface has inverted from the p-type polarity of the original substrate to an n-type For the enhance mode, Vin > 0 and Vip <0

II) Transconductance parameters

k and k’ are called transconductance parameters, both have units of A/V* The & can be estimated as the slope of from equation (S1) or equation (S2)

II) Body effect coefficient

When a non-zero substrate bias voltage (Vsp) is applied It has a huge effect on the threshold voltage, thus introducing the body effect coefficient , which can be found from:

Where Vr: the threshold voltage when a non-zero Vss is applied Vi: threshold voltage when Vs = OV, : substrate Fermi potential

Note that the substrate bias coefficient is positive in NMOS and negative in PMOS

IV) Channel length modulation coefficient parameter

Without neglecting the channel length modulation effect The Equation(S1) or Equation (S2) can be explained as follows:

The experiment measurement of the requires different test circuit setups The Ves is set to Vro +1 The Vps is chosen sufficiently large so that the transistor operates in saturation mode The Ip sa is measured for two different drain voltage values, Vosi and Vps2 Since Ves = Vo +1, the ratio of the measured drain current values 1s:

V) CD4007 pinout

CD4007 is comprised of three n-channel and three p-channel enhancement MOS transistors The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits

SCHEMATIC

14 13 2 1 "

; }

7 8 3 4 5 4

Vọo = PIN 14

Vgg = PINT

VI) Common-Source Amplifier

@ FET is a Voltage - controlled device

@ The CS Amplifier circuit includes the characteristics:

¢ Has relatively high Voltage and Current gain

¢ Input impedance is high > Input current I, is very small

« Relatively high output impedance

Ip

Var

C;

VIN o—)

+

Figure 1: Basic circuit for CS Amplifier

Cutoff region

Vos <V, >i, =0 Triode region

Ves 2V, and vy SVs —V, Sip =k, L [es Ys ~5V/sl

for sufficiently small v,, DS > i,, * k, 0w —V Wy

w W _ ps —— , 1

—> ly =— i, =[k,, L (VEs =F,)|

Saturation region

1N „v3

Ves 2 V, and Vos 2 Ves — V, Ip =F ha Wes -] i)

ip(mA) J

S te — V,

"ps Tran Me Ị Mps = tọs — V;

—= region —>›“<———— SŠaturation region —————> Ị

/

he uns = ugs — V, /

vas = V, +3

0 13234 5 6 7 a Ups (V)

tgs = V, (cut off)

Figure 2: Characteristic DC load line

Ip (mA)

Ip = Vop 5

D A

DC Load Line ASS oy

¬

Ves = -0.4v

mn Ves 0.6v

Ti Ves = -0.8v

Voo

Figure 3: Characteristic DC load line

» FET is a Voltage - controlled device with three terminals G, D and S

X Characteristics DC load line:

> The output signal is 180° out of phase with the input signal

VI) CS Amplifier DC Analysis

International University School of Electrical Engineering

Figure 5: CS Amplifier AC analysis

2 Experimental Procedure

- Introduced to:

The Common Source and Common Drain Amplifier circuits

The process of DC and AC Analysis in measurement

Examine different conditions in AC signal amplification of the above circuits The application of those concepts in simulation program

2.1 Common-Source Amplifier

For this experiment, we prepare the basic common-source (CS) circuit:

MAA vy >

AAAA VVV¥

<

~

dl AAA yy

Figure 6: Circuit diagram 2

In comparison to the BJT common-emitter amplifier, the FET amplifier has a much higher input impedance, but a lower voltage gain

Use Col = 0.1 uF, Cco2 = 1uF, Cs= 0.1 uF, Rs = 1kQ, Ro= 47 kQ, Ri= 200kQ, R2 =100 kQ, Vpp= 12V

Apply a sinusoidal signal with frequency 1kHz, amplitude 0.4Vp-p

2.1.1 Sub-task 1

Observe the output

2.1.2 Sub-task 2

Capture both input and output waveforms

2.1.3 Sub-task 3

Calculate the voltage gain

2.1.4 Sub-task 4

Perform a frequency sweeping from 1Hz to 100KHz Plot the frequency response of voltage gain 2.1.5 Sub-task 5

a Connect Ca = 1uF to the Drain terminal Capture the waveforms and measure the gain Then, connect the load resistor Rt =1 kQ, one pin is connected to the capacitor C2, the other pin is connected to the ground Perform a parameter sweep on Ri from 1K Ohm to 100K ohm observe the effects of Ry on the Vou of the circuit, and comment on results Assume that Vin does not change, compute the gains based on the change in the value of

Ra

3 Experimental Results

3.1 Experiment 1

b) Capture both input and output waveforms

Memory (ime 225 sins

STELLAR

Figure 7: Waveform of input and output c) Calculate the voltage gain (15.97)

d) Perform a frequency sweeping from 1Hz to 100KHz Plot the frequency response of voltage gain ( ) dB

Frequency | Gain | Frequency | Gain | Frequency | Gain | Frequency | Gain

100 | 13.75 1000 15.97 10,000 15.59 60,000 11.89

200 | 14.28 2000 16.11 20,000 15 70,000 10.98

400 14.7 3000 16.02 30,000 14.16 80,000 10.4

600 | 15.07 4000 15.88 40,000 13.17 90,000 99

800 | 15.34 5000 15.83 50,000 12.4 100,000 9.437

Table 1: Data of experiment 1

e) Capture the waveforms and measure the gain Then, connect the load resistor Rt =1 kQ, one pin is connected to the capacitor C2, the other pin is connected to the ground Perform a parameter sweep on R, from 1 KOhm to 100 Kohm observe the effects of on the Vout of the circuit, and comment on results

Figure 4: Waveform of input and output

(Simulation) | (Measurement) (Simulation) | (Measurement)

4.7K 711 -2.47 100K 14.43 13.42

Table 3: Data of experiment 1

Designt

RL Parameter Sweep from 1kO to 100kO

Figure 8: Waveform of input and output of simulation Comment: The gain (in dB) tends to increase of of CS Amplifier when the value of RL is larger Therefore, increasing RL will increase Av, while decreasing RL will decrease Av However, there are some limits to how much RL can be changed without affecting the operation of the NMOSFET

4 Discussion of Results

In this final lab session, finally my team can do the lab completely done with minor mistakes left With major help of our handsome assistant my team corrected the issues immediately during the lab to practiced it hard before examination I hope my team can do the examination as well and as good as today lab Thanks again to my best teamates and my handsome lab assistant I hope to see you guys soon in the next coming lab courses