Bài tập chương 3 Đại số Boole & Các cổng luận lý BK TP HCM 2011 dce Exercise – Chapter 5 Flip Flop Nguyễn Quang Huy huynguyen@cse hcmut edu vn mailto huynguyen@cse hcmut edu vn 2011 dce 5 1 • Assuming[.]
dce 2011 Exercise – Chapter Flip Flop BK TP.HCM Nguyễn Quang Huy huynguyen@cse.hcmut.edu.vn dce 2011 5.1 • Assuming that Q = initially, apply the x and y waveforms to SET and CLEAR inputs of a NAND latch, determine the Q and Q’ Exercise Chapter - Flip Flop dce 2011 5.2 • Invert x and y waveforms, apply to SET and CLEAR inputs of a NOR latch, determine Q and Q’, assume Q = initially Exercise Chapter - Flip Flop dce 2011 5.3 • Q = initially, determine Q waveform Exercise Chapter - Flip Flop dce 2011 5.4 • Modify the circuit to use a NOR gate latch Exercise Chapter - Flip Flop dce 2011 5.5 • Modify the circuit (Figure 5.12) to use a NAND gate latch Exercise Chapter - Flip Flop dce 2011 5.9 • Apply the waveforms to FF in Figure 5-17, 5-18 Assume Q = initially Exercise Chapter - Flip Flop dce 2011 5.11 • Apply a 10-kHz clock signal to CLK of a J-K FF that has J = K = Determine the waveform at Q • Connect Q this FF to CLK of a 2nd J-K FF that also has J = K = Determine the frequency of the signal at this FF’s output Exercise Chapter - Flip Flop dce 2011 5.12 • Positive/Negative-edge-triggered J-K Exercise Chapter - Flip Flop