Compal La-B071P Rev1.0.Pdf

MARBLE FALLS LA B071P UMA 0730 pdf 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Dell / Compal Confidential Intel HSW/BDW ULT Marble Falls 14"/15" Value UMA 2014 07 17 Rev 1 0 Schematic Document MODEL NAME Marb[.]

5 MODEL NAME : Marble Falls/ UMA PROJECT CODE : ZAL50, ZAL60 PCB NO : LA-B071P D D ZZZ R1@ UC1 PCB 14B LA-B071P REV0 M/B CPU C C Dell / Compal Confidential Schematic Document Intel HSW/BDW ULT Marble Falls 14"/15" Value UMA B 2014-07-17 B Rev: 1.0 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/08/01 Deciphered Date 2014/07/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Cover Page Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet of 47 D D eDP Conn eDP Page 21 HDMI Conn Memory Bus (DDR3L) DDI Dual Channel Page 19 CRT Conn DP to CRT IT6513FN Page 20 DDI DDRIII-DIMM X2 BANK 0, 1, 2, 3, ,5 ,6 ,7 1.35V DDR3 1600 MHz Page 17, 18 8GB Max Page 20 USB 3.0 Intel HSW/BDW ULT-U USB2.0 Processor BGA 1168 Port Port Port Port USB 3.0 Conn Page 24 USB 3.0 Conn Page 24 C C Port PCI-E Port x1 x1 Port Port NGFF 2230 WiFi/BT4.0 Ethernet RTL8111GUS-CG Page 25 Page 22 Fingerprint NGFF WiFi/BT4.0 Port Digital Camera (With Digital MIC) Page 21 SATA HDD Conn Page 26 Port SATA Rediver Page 25 Touch Screen Port Page 27 Page 26 Port Port USB 2.0 Conn Card Reader RTS5176E Page 21 Page 27 SATA3.0 Page 26 B B Digital Mic HD Audio LS-B071P Audio Codec ALC3234 USB2.0 Conn USB2.0 Port SPI ROM 8MB Card Reader IOR/B Headphone Jack / Mic Jack combo Page 23 Page 23 Int Speaker R / L SPI Page 23 Page 6~16 Page USB2.0 Port LPC Bus ϯϯD,nj LS-B072P LED *2 SMSC SIO ECE1099 Page 28 A BC Bus SMSC KBC MEC5085 PS/2 Touch Pad Page 29 Page 27 KBD Lid Switch BC bus LED/B KB control ECE1117 Page 30 KB BKL Page 30 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date A Page 30 2013/08/01 Deciphered Date 2014/07/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Block diagram Size Document Number Rev 1.0 LA-B071P Date: Wednesday, July 30, 2014 Sheet of 47 D D IOR /B :h^ϯ C :Z 3in1 16pin :/Kϭ FFC pin :/K pin pin :> >ŝĚ^ǁŝƚĐŚ B >Ϯ :>ϭ C pin 8pin N C B >ϭ LED /B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/08/01 2014/07/31 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: DB block diagram Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet of 47 Board ID Table USB3.0 Phase ID RE79 D CE54 REV 240K 4700p 130K 4700p 62K 4700p 33K 4700p 8.2K 4700p 4.3K 4700p 2K 4700p 1K 4700p X00 X01 X02 X03 A00 Port2 USB connector D Port4 USB2.0 Config ID RE89 RE90 De-Pop Pop Discrete Pop De-Pop UMA Port0 USB connector Port1 USB connector Port2 USB connector (IO/B) Port3 Finger print Port4 NGFF (BT + WLAN) Port5 Touch Screen Panel Port6 Card Reader Port7 Camera Config SMBUS Control Table SOURCE BATT Charger CHARGER_SMBCLK MEC5085 CHARGER_SMBDAT PBAT_SMBCLK PBAT_SMBDAT USB connector Port3 KZͺ/ƌŝƐĞƚŝŵĞŝƐŵĞĂƐƵƌĞĚĨƌŽŵϱйΕϲϴй͘ C Port1 MEC5085 DDR3L XDP WLAN NGFF Touch pad ULT V V C PCI EXPRESS SML1_SMBCLK SML1_SMBDATA Lane SMBCLK SMBDATA ULT SML0CLK SML0DATA ULT Lane SML1CLK SML1DATA ULT Lane 10/100/1000 LAN Lane NGFF (BT + WLAN) V V V V Link Lane B CLOCK SIGNAL B Lane CLKOUT_PCIE0 SATA CLKOUT_PCIE1 SATA0 CLKOUT_PCIE2 10/100/1000 LAN CLKOUT_PCIE3 NGFF (BT + WLAN) SATA1 6\PERO1RWH SATA2 PHDQV'LJLWDO*URXQG CLKOUT_PCIE4 CLKOUT_PCIE5 HDD SATA3 DDI PHDQV$QDORJ*URXQG A HDMI DDI2 DP to CRT A Compal Electronics, Inc Compal Secret Data Security Classification Issued Date DDI1 2013/08/01 2014/07/31 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Notes List Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet of 47 2.2K SMBUS Address [0x9a] 2.2K D AP2 MEM_SMBCLK AH1 MEM_SMBDATA 2.2K +3.3VALW_PCH +3VS 2.2K N-MOS N-MOS DDR_XDP_WLAN_TP_SMBCLK 202 DDR_XDP_WLAN_TP_SMBDAT 200 DIMMA D SMBUS Address [A0] 1K 202 +3.3VALW_PCH 1K MCP AN1 SML0CLK AK1 SML0DATA ohm ohm 2.2K 2.2K AN1 SML1_SMBCLK AK1 SML1_SMBDATA DIMMB SMBUS Address [A4] 200 DDR_XDP_SMBCLK_R1 53 DDR_XDP_SMBDAT_R1 51 JXDP1 SMBUS Address [TBD] +3.3VALW_PCH C C 79 SML1_SMBCLK 80 SML1_SMBDATA 2.2K 2.2K MEC 5085 B 77 CHARGER_SMBCLK 78 CHARGER_SMBDAT +3VALW_5085 ohm ohm SCL 11 SDA 10 PU700 POWER Charger SMBUS Address [0x12] B 2.2K 2.2K +3VALW_5085 PBAT_SMBCLK PBAT_SMBDAT 100 ohm 100 ohm PD1 Z4304 Z4305 PBATT1 BATT SMBUS Address [0x16] CONN A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/08/01 Deciphered Date 2014/07/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SMBus block diagram Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet of 47 0.1U_0402_10V7K 14 PCH_JTAG_TDO @ [8] PCH_JTAG_TDI @ RC44 TDI_XDP 0_0402_5% RC45 [8] PCH_JTAG_TMS @ RC46 CC29 ESD@ 0.1U_0402_10V7K 4A 4B 4OE GND GND PAD XDP_PREQ# XDP_PRDY# XDP_TDI Place near JXDP1 [16] [16] CFG0 CFG1 [16] [16] CFG2 CFG3 CFG3 XDP_OBS0_R XDP_OBS1_R XDP_TMS 11 [13] XDP_TRST# RC114 H_VCCST_PWRGD 1K_0402_5% H_CPUPWRGD [10,29] SIO_PWRBTN# [13] CPU_PWR_DEBUG# [10,29] SYS_PWROK 15 [9,17,18] [9,17,18] 74CBTLV3126BQ_DHVQFN14_2P5X3 2 ZϱŶĞĞĚƚŽĐůŽƐĞƚŽ:Whϭ 13 SYS_PWROK DDR_XDP_WLAN_TP_SMBDAT DDR_XDP_WLAN_TP_SMBCLK reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0 [16] [16] CFG4 CFG5 [16] [16] CFG6 CFG7 RC48 RC49 @ @ 1K_0402_5% 0_0402_1% H_VCCST_PWRGD_XDP CFD_PWRBTN#_XDP RC50 RC52 @ @ 0_0402_1% 0_0402_1% CPU_PWR_DEBUG#_R SYS_PWROK_XDP RC53 RC54 @ @ 0_0402_1% 0_0402_1% DDR_XDP_SMBDAT_R1 DDR_XDP_SMBCLK_R1 PCH_JTAG_TCK XDP_TCLK +3VALW_PCH 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 CFG17 CFG16 CFG8 CFG9 2 PCH_JTAG_JTAGX @ @ 0_0402_5% [16] [16] [16] [16] D XDP_RST#_R XDP_DBRESET# CFG10 CFG11 [16] [16] CFG19 CFG18 [16] [16] CFG12 CFG13 [16] [16] CFG14 CFG15 [16] [16] 2 RC51 1K_0402_5% TDO_XDP TRST#_XDP TDI_XDP TMS_XDP CFG3_R RC56 CFG3 1K_0402_5% XDP_DBRESET# XDP_TRST# RC57 PCH_PLTRST#_EC +3VS [10,22,25,29] RC362 1K_0402_1% CC17 0.1U_0402_10V7K SAMTE_BSH-030-01-L-D-A CONN@ PCH_JTAG_RST# 0_0402_5% PCH_JTAG_RST# [8] 3B Place CC29 close to UC4 [8] 3OE 12 RUNPWROK RUNPWROK 2B 3A 10 TRST#_XDP XDP_TDO 2OE TMS_XDP 0_0402_5% RUNPWROK [29] 2A RUNPWROK 1B +1.05VS JXDP 1OE TDI_XDP_R 0_0402_5% 1A RUNPWROK D VCC TDO_XDP 0_0402_5% +1.05VS XDP_DBRESET# [10] RC64 1K_0402_5% XDP_TCLK RC59 [8] @ CC15 0.1U_0402_10V7K XDP@ @ CC14 0.1U_0402_10V7K UC4 @ +1.05VS +3VS CC13 1 PCH_JTAG_TDO RC43 SYS_PWROK_XDP 0_0402_5% C PCH_JTAG_TDO 0_0402_5% [8] 0_0402_5% TDI_XDP_R RC63 @ PCH_JTAG_TCK TDO_XDP RC62 @ XDP_TCLK RC65 @ DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 [20] [20] [20] [20] DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 C Place near JXDP1.47 HASWELL_MCP_E UC1A [19] [19] [19] [19] [19] [19] [19] [19] @ CC16 0.1U_0402_10V7K DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 C54 C55 B58 C58 B55 A55 A57 B57 C51 C50 C53 B54 C49 B50 A53 B53 DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 DDI EDP DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL C45 B46 A47 B47 EDP_TX0# EDP_TX0 EDP_TX1# EDP_TX1 [21] [21] [21] [21] C47 C46 A49 B49 COMPENSATION PU FOR eDP A45 B45 D20 A43 EDP_AUX# EDP_AUX EDP_COMP EDP_DISP_UTIL RC72 +VCCIOA_OUT [21] [21] @ 0_0402_5% EDP_BIA_PWM [10,21] 24.9_0402_1% RC71 CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils B B OF 19 Rev1p2 @ +1.05VS HASWELL_MCP_E UC1B 2 @ RC58 RC60 H_CATERR# 49.9_0402_1% H_PROCHOT# 62_0402_5% D61 K61 N62 H_CATERR# [29] PECI_EC PROC_DETECT CATERR PECI MISC JTAG H_PROCHOT# H_PROCHOT#_R 56_0402_5% K63 H_CPUPWRGD C61 RC66 10K_0402_5% 2 EMI@ CA26 22P_0402_50V8J PROCHOT PROCPWRGD [29,38,41] RC67 H_PROCHOT# AU60 AV60 AU61 AV15 AV61 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DDR3_DRAMRST#_CPU [17] DDR_PG_CTRL CC35 BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 DDR3 OF 19 @ 0.047U_0402_16V4Z A SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 J62 K62 E60 E61 E59 F63 F62 XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO J60 H60 H61 H62 K59 H63 K60 J61 XDP_OBS0_R XDP_OBS1_R +1.05VS PU/PD for JTAG signals XDP_TMS XDP_TDI XDP_PREQ# TDO_XDP PWR CC27 100P_0402_50V8J ESD@ ESD solution [17] THERMAL PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO T111 T112 T113 T114 T115 T116 RP44 @ 51_8P4R_5% @ @ @ @ @ @ XDP_TDO XDP_TCLK RC366 RC367 1 51_0402_5% 51_0402_5% XDP_TRST# 51_0402_5% @ RC129 Rev1p2 @ A DDR3 COMPENSATION SIGNALS 200_0402_1% RC68 SM_RCOMP0 121_0402_1% RC69 SM_RCOMP1 100_0402_1% RC70 SM_RCOMP2 Place CC35 on BOT Issued Date Compal Electronics, Inc Compal Secret Data Security Classification CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil 2013/08/01 Deciphered Date 2014/07/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: MCP(1,2/19) eDP,XDP,MISC Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet of 47 /ŶƚĞƌůĞĂǀĞĚDĞŵŽƌLJ UC1C D [17] [18] [17] DDR_A_D[0 15] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D[0 15] DDR_A_D[16 31] C [18] DDR_B_D[16 31] AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 [17] HASWELL_MCP_E HASWELL_MCP_E UC1D DDR_A_D[32 47] D SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 AU43 AW43 AY42 AY43 DDR_CKE0_DIMMA DDR_CKE1_DIMMA AP33 AR32 DDR_CS0_DIMMA# DDR_CS1_DIMMA# M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 [17] [17] [17] [17] DDR_CKE0_DIMMA DDR_CKE1_DIMMA [17] [17] DDR_CS0_DIMMA# DDR_CS1_DIMMA# [17] [17] AP32 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 AY34 AW34 AU34 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# AU35 AV35 AY41 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 DDR CHANNEL A AU37 AV37 AW36 AY36 SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# DDR_A_BS0 [17] DDR_A_BS1 [17] DDR_A_BS2 [17] DDR_A_MA[0 15] DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 [18] AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48 DDR_A_DQS#0 DDR_A_DQS#1 DDR_B_DQS#0 DDR_B_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_B_DQS#2 DDR_B_DQS#3 AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49 DDR_A_DQS0 DDR_A_DQS1 DDR_B_DQS0 DDR_B_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_B_DQS2 DDR_B_DQS3 DDR_B_D[32 47] [17] [17] DDR_A_DQS#[0 1] [17] DDR_B_DQS#[0 1] [18] DDR_A_DQS#[2 3] [17] DDR_B_DQS#[2 3] [18] [18] AP49 AR51 AP51 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 [17] [17] [17] DDR_A_DQS[0 1] [17] DDR_B_DQS[0 1] [18] DDR_A_DQS[2 3] [17] DDR_B_DQS[2 3] [18] DDR_A_D[48 63] DDR_B_D[48 63] +SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1 AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 AY49 AU50 AW49 AV50 DDR_CKE2_DIMMB DDR_CKE3_DIMMB AM32 AK32 DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 [18] [18] [18] [18] DDR_CKE2_DIMMB DDR_CKE3_DIMMB [18] [18] DDR_CS2_DIMMB# DDR_CS3_DIMMB# [18] [18] AL32 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2 DDR CHANNEL B AM38 AN38 AK38 AL38 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 AM35 AK35 AM33 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18 DDR_A_DQS#4 DDR_A_DQS#5 DDR_B_DQS#4 DDR_B_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_B_DQS#6 DDR_B_DQS#7 AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18 DDR_A_DQS4 DDR_A_DQS5 DDR_B_DQS4 DDR_B_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_B_DQS6 DDR_B_DQS7 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# [18] [18] [18] DDR_B_BS0 [18] DDR_B_BS1 [18] DDR_B_BS2 [18] DDR_B_MA[0 15] [18] C DDR_A_DQS#[4 5] [17] DDR_B_DQS#[4 5] [18] DDR_A_DQS#[6 7] [17] DDR_B_DQS#[6 7] [18] DDR_A_DQS[4 5] [17] DDR_B_DQS[4 5] [18] DDR_A_DQS[6 7] [17] DDR_B_DQS[6 7] [18] B B OF 19 OF 19 Rev1p2 Rev1p2 @ @ 2 CC9 0.022U_0402_16V7K RC19 2.2_0402_1% RC22 1.82K_0402_1% change 22nF RC24 24.9_0402_1% +SM_VREF_DQ0 RC18 2.2_0402_1% RC21 1.82K_0402_1% change 22nF CC10 0.022U_0402_16V7K change 22nF RC25 24.9_0402_1% 2 RC23 24.9_0402_1% RC16 1.82K_0402_1% RC20 1.82K_0402_1% CC8 0.022U_0402_16V7K 1 +SM_VREF_DQ0_DIMM1 1 RC17 2.2_0402_1% +SM_VREF_DQ1 RC15 1.82K_0402_1% 1 +SM_VREF_DQ1_DIMM2 +SM_VREF_CA RC14 1.82K_0402_1% +SM_VREF_CA_DIMM +1.35V +1.35V +1.35V confirm by intel request PDG P141 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/08/01 Deciphered Date 2014/07/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: MCP(3,4/19) DDR3 Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet of 47 +RTCVCC JRTC RC10 1K_0402_5% +CHGRTC 2 GND GND +3VALW_PCH PCH_INTVRMEN D RC9 1K_0402_5% W=20mils PJP12 DC1 BAT54CW_SOT323-3 +CHGRTC 2 1 ME_EN +3VLP [29] JUMP_43X39 @ ME_FWP_EC G G SW3 @ W=20mils ME_FWP_EC 0_0402_5% ME_EN RC375 ACES_50271-0020N-001 CONN@ D @ RC2 330K_0402_1% ^ĞƌǀŝĐĞDŽĚĞ^ǁŝƚĐŚ͗ ĚĚĂƐǁŝƚĐŚƚŽDͺ&tWƐŝŐŶĂůƚŽƵŶůŽĐŬƚŚĞDƌĞŐŝŽŶĂŶĚ ĂůůŽǁƚŚĞĞŶƚŝƌĞƌĞŐŝŽŶŽĨƚŚĞ^W/ĨůĂƐŚƚŽďĞƵƉĚĂƚĞĚƵƐŝŶŐ&Wd͘ +RTCBATT +RTCBATT RC1 330K_0402_1% RTC Battery @ SSAL120100_3P /EdsZDEͲ/Ed'Zd^h^ϭ͘ϬϱssZD E> ,ŝŐŚͲŶĂďůĞ/ŶƚĞƌŶĂůsZƐ >ŽǁͲŶĂďůĞdžƚĞƌŶĂůsZƐ +RTCVCC W=20mils Dͺ&tWW,ŚĂƐŝŶƚĞƌŶĂůϮϬ;&h>dͿ R2337 R2338 PCH_RSMRST#_R 10K_0402_5% [6,29] [13,29] RESET_OUT# ^tKsZEͲKE/^tsZE> HASWELL_MCP_E UC1H DSWODVREN RC97 @ CLKRUN# @ PCH_DPWROK PCH_PCIE_WAKE# 0_0402_5% [29] [28,29] [29] 0_0402_5% SIO_SLP_S5# [29] SIO_SLP_S4# SIO_SLP_S3# [29] [29] SIO_SLP_SUS# SUSCLK [25] [29] Rev1p2 @ +3VS B +3VS [6,21] RP43 SIO_RCIN# PCH_GPIO36 DGPU_PWROK PCH_GPIO80 [21] SIO_RCIN# PCH_GPIO36 EDP_BIA_PWM PANEL_BKLEN [11,29] [8] [21,29] 10K_8P4R_5% @ EDP_BIA_PWM 10K_0402_5% @ ENVDD_PCH 100K_0402_5% RC75 RC87 EDP_BIA_PWM RC81 @ ENVDD_PCH [11] PCH_GPIO77 [11] PCH_GPIO79 @ @ EDP_BKLCTL 0_0402_5% ENVDD_PCH T199 T200 PCH_GPIO77 DGPU_PWROK PCH_GPIO80 @ T117 DGPU_PWR_EN DGPU_CORE_EN B8 A9 C6 U6 P4 N4 N2 AD4 U7 L1 L3 R5 L4 B HASWELL_MCP_E UC1I EDP_BKLCTL EDP_BKLEN EDP_VDDEN PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND DISPLAY GPIO GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP DDPB_HPD DDPC_HPD EDP_HPD B9 C9 D9 D11 CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT C5 B6 B5 A6 CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX C8 A8 D6 CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_AUX# CPU_DPC_AUX DPB_HPD [19] DPC_HPD [20] CPU_EDP_HPD DPC_HPD CPU_EDP_HPD [19] [19] [20] CPU_DPB_CTRLDAT CPU_DPB_CTRLCLK CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT RP52 2.2K_8P4R_5% CPU_DPB_AUX# CPU_DPB_AUX CPU_DPC_AUX CPU_DPC_AUX# [20] RP51 100K_8P4R_5% DPC_HPD RC84 @ CPU_EDP_HPD RC89 OF 19 100K_0402_5% [21] 100K_0402_5% Rev1p2 @ A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/08/01 Deciphered Date 2014/07/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: MCP(8,9/19) DDI,EDP,GPIO Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet 10 of 47 A B C D EMI@ PL8 HCB2012KF-121T50_0805 EMI@ PL1 HCB2012KF-121T50_0805 EMI@ PL2 HCB2012KF-121T50_0805 PBATT+_C 1000P_0402_50V7K EMI@ PC1 1 2 EMI@ PC3 0.01U_0402_25V7K 1 +PBATT EMI@ PD2 TVNST52302AB0_SOT523-3 EMI@ PD1 TVNST52302AB0_SOT523-3 3 LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2 1 2 BAT_ALERT 4 BATT_PRS DAT_SMB CLK_SMB 8 9 10 GND 11 GND PR2 EMI@ PC2 2200P_0402_50V7K 60$57 %DWWHU\ *1' *1' %$7B$/(57 6Kͺϯs @ PJP300 +1.05VSP PU300 EMI@ PC303 2200P_0402_50V7K н @ PC301 @ PR302 680P_0603_50V7K 4.7_1206_5% 2SNB_1.05V 1 EMI@ PL302 HCB2012KF-121T50_0805 VFB=0.6V Vout=0.6V* (1+Rup/Rdown) Vout=1.05V +1.05VSP TDC 5A Peak Current 6.6A OCP current 8A A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/10 Deciphered Date 2014/05/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+VCCIO Size Document Number Rev 1.0 LA-B071P Date: Wednesday, July 30, 2014 Sheet 39 of 47 1 PC908 22U_0805_6.3V6M 2 PC916 22U_0805_6.3V6M PC907 22U_0805_6.3V6M 2 PC915 22U_0805_6.3V6M PC923 22U_0805_6.3V6M PC906 22U_0805_6.3V6M PC914 22U_0805_6.3V6M PC922 22U_0805_6.3V6M PC905 22U_0805_6.3V6M PC913 22U_0805_6.3V6M 2 PC921 22U_0805_6.3V6M 1 PC904 22U_0805_6.3V6M 2 PC920 22U_0805_6.3V6M @ @ D @ C PC947 0.1U_0402_10V7K @ PC912 22U_0805_6.3V6M PC903 22U_0805_6.3V6M PC911 22U_0805_6.3V6M PC919 22U_0805_6.3V6M @ PC946 0.1U_0402_10V7K 1 PC910 22U_0805_6.3V6M 2 @ @ PC945 0.1U_0402_10V7K @ PC944 0.1U_0402_10V7K 1 2 C PC943 0.1U_0402_10V7K PC917 22U_0805_6.3V6M PC909 22U_0805_6.3V6M @ PC918 22U_0805_6.3V6M PC901 22U_0805_6.3V6M D PC902 22U_0805_6.3V6M +CPU_CORE @ B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/10 Deciphered Date 2014/05/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PWR_PROCESSOR DECOUPLING Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet 40 of 47 B BQ24777_REGN GNDA_CHG GNDA_CHG 14 15 16 29 [29,33] PBAT_PRES# CHG_UGATE CHG_SW PHASE 23 CHG_LGATE PC710 10U_0805_25V6K PC711 10U_0805_25V6K PC709 10U_0805_25V6K EMI@ PC725 0.1U_0603_25V7K PC731 10U_0805_25V6K PC708 10U_0805_25V6K EMI@ PC724 0.1U_0603_25V7K PC730 10U_0805_25V6K PC707 10U_0805_25V6K PC706 10U_0805_25V6K PC717 10U_0805_25V6K EMI@ PC723 0.1U_0603_25V7K PC705 10U_0805_25V6K @ @ BAT_B+ PR710 0.01_1206_1% PL701 2.2UH_12A_20%_10X10X4_M PC732 10U_0805_25V6K @ NC CMPIN 22 21 PR706 10K_0402_1% BQ24777_REGN CMPOUT /BATPRES CELL SRN /BATDRV PWPD BAT 20 19 17 PC729 1U_0603_25V6K GNDA_CHG PJP701 PR704 4.02K_0402_1% 18 PC726 0.1U_0402_25V6 PC727 0.1U_0402_25V6 PC721 10U_0805_25V6K GND @ PC752 0.1U_0603_25V7K PMON /PROCHOT PC720 10U_0805_25V6K 2 LODRV IDCHG BQ24777RUYR_WQFN28_4x4 PR728 0_0402_5% @ PQ704 SIR472DP-T1-GE3_POWERPAK8-5 ACP 26 27 IADP SRP H_PROCHOT# PR725 1K_0402_1% 10 13 [6,29,38] PR717 0_0402_5% @ PR732 20K_0402_1% @ 0_0402_5% 0_0402_5% 0_0402_5% I_SYS @ @ [29] I_BATT PR716 PR718 PR720 [29] I_ADP PC719 100P_0402_50V8J 2 [29] PR715 154K_0402_1% PC718 100P_0402_50V8J ACAV_IN [29] ACOK @ PR711 4.7_1206_5% HIDRV @ PC722 1000P_0603_50V7K CHARGER_SMBCLK SDA SCL CHARGER_SMBDAT [29] CHG_BTS_C CHG_SNUB [29] BTST PR712 2.2_0603_5% 25CHG_BTS PQ705 SIRA06DP-T1-GE_POWERPAKSO-8-5 GNDA_CHG ACDET 24 11 12 1U_0603_10V6K REGN CMSRC @ @ PC751 BQ24777_REGN PC750 0_0402_5% 0_0402_5% VCC 0.1U_0402_25V6 PR713 100K_0402_1% PR714 0_0402_5% @ 28 ACDET PR719 PR721 PU700 +DCIN @ PC728 0.1U_0402_25V6 GNDA_CHG GNDA_CHG PR723 10_0603_1% PR740 6.49K_0402_1% PC748 1U_0603_25V6K GNDA_CHG ACN S PQ709 DMN65D8LW-7_SOT323-3 ACDRV CHARGER_SMBCLK CHARGER_SMBDAT pull up 10K in HW side (R827 R828) 1BQ24777_REGN PR741 100K_0402_1% G PR739 34K_0402_1% D 1 2 PC747 0.1U_0402_25V6 GNDA_CHG PR708 PR730 10_1206_5% 4.02K_0402_1% [29] AC_DIS PC746 0.1U_0402_25V6 PC712 0.047U_0603_25V7K~D B+ PC745 1U_0603_25V6K 1 +DC_IN PC716 10U_0805_25V6K CSSN_1 CSSP_1 +DC_IN @ @ @ PR705 0_0402_5% 2 PD703 SDMK0340L-7-F_SOD323-2 @ PR738 0_0402_5% 4.02K_0402_1% PR731 PD702 SDMK0340L-7-F_SOD323-2 +PBATT @ PQ708A DCX124EK-7-F_SC74R-6 EMI@ PL700 1UH_6.6A_20%_5X5X3_M 2 PC704 10U_0805_25V6K @ PC703 2200P_0402_50V7K 1 PC701 0.1U_0402_25V6 PR737 4.7_0402_1% @ PQ708B DCX124EK-7-F_SC74R-6 CHAGER_SRC @ PC734 10U_0805_25V6K 0.022U_0603_50V7K PC700 MDU1516URH_POWERDFN56-8-5 0708 PR748 change from SE000001380to SE000006900 PC701,PC750 change from SE00000DR00 to SE00000G880 +PWR_SRC_AC PR702 0.01_1206_1% @ PC702 0.1U_0402_25V6 +SDC_IN PQ702 MDS1525URH_SO8 PQ701 D +DC_IN_SS +DC_IN C A 3%$77 BATDRV# GNDA_CHG @ PR729 121K_0402_1% PAD-OPEN1x1m GNDA_CHG GNDA_CHG 3 PQ703 AO4407AL_SO8 +PBATT BAT_B+ BATDRV# 4 DELL CONFIDENTIAL/PROPRIETARY Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/10 Deciphered Date 2014/05/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_Charger_BQ24777 Size B C Document Number Rev 1.0 LA-B071P Date: A Wednesday, July 30, 2014 D Sheet 41 of 47 Power block D Input Switch Page 41 DC IN D B+ +3VALWP: TDC:2.76A +5VALWP: TDC:6.86A TPS51285BRUKR ALWON Page 34 C C +3VALW CHARGER BQ24777(NVDC) +1.5VSP: TDC:3A APL5930KAI RUN_ON Page 36 Page 41 +1.35VP/+0.675VSP: TDC:8.4A/0.7A G5616ARZ1U Page 37 Battery CC:2A(3cell) or 3.9A(4cell) CV:13.2V(3cell) / 8.7V(4cell) SUS_ON 0.675V_DDR_VTT_ON +VCCIO: TDC:5A SY8206DQNC RUN_ON Page 39 B B CPU_CORE: TDC 16A@28W CPU ISL95813HRZ-T VR_ON Page 38 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/10 Deciphered Date 2014/05/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PWR_POWER BLOCK DIAGRAM Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet 42 of 47 V ersion Change L ist ( P I R L ist ) Item P age# T itle D ate R equest O w ner Page Issue D escription P33 DCIN/BATT CONN/OTP 2013/11/12 PWR EMI requirement Add PL5/PL7(SM01000C000) P33 DCIN/BATT CONN/OTP 2013/11/12 PWR EMI requirement P40 PROCESSOR DECOUPLING 2013/11/12 PWR SSI verify , Vcore keep 18 keep Add PL8(SM01000C000), PL1/PL2/PL5/PL6 change from SM010009C80 to SM01000C000 for finding 2nd source easily PC901,PC907,PC923,PC912,PC903 change from pop to de-pop P41 Charger_BQ24777 2013/11/12 PWR P38 VCORE 2013/11/12 PWR P38 VCORE 2013/11/12 PWR change to Vendor (CYNTEC) PL502 change to SH00000PQ00 P34 3.3VALWP/5VALWP 2013/11/12 PWR EMI requirement and current rating add PL103 (SM01000C000) P38 VCORE 2013/11/12 PWR EMI requirement add PL504(SM01000C000) P38 VCORE 2013/11/12 PWR EMI requirement PL501 change from SM010009C80 to SM01000C000 10 P34 3.3VALWP/5VALWP 2013/11/13 PWR for common part PL100 change from SH00000MS00 to SH00000YC00 EMI requirement PL502 change from 0.22uH to 0.15uH P37 +1.35VP/0.675VSP 2013/11/13 PWR for common part PL200 change from SH00000KS00 to SH00000YE00 12 P39 +VCCIO 2013/11/15 PWR EMI requirement PL302 change form SM010009C80 to SM01000C000 13 P33 DCIN/BATT CONN/OTP 2013/11/21 PWR ESD requirement add PD3 (AZ5125-01H.R7G_SOD523-2) 14 P34 3.3VALWP/5VALWP 2013/11/21 PWR change to same material PD101 change from SCA00002A00 to SCA00001W00 15 P41 Charger_BQ24777 2013/11/21 PWR peak shift issue Add PQ709 16 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PR535 change from 340 ohm to 255 17 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PR537 change from 1.27k to 1.58k 18 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PC527 from pop to de-pop 19 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PR543 change from pop to de-pop 20 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PC529 change from 0.047u to 0.068u 21 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PR551 change from 2.61k to 4.42k 22 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PR539 change from 8.06k to 3.16k 23 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PC531 chnge from pop to de-pop 24 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PR507 change from 90.9k to 205k 25 P38 VCORE 2013/11/21 PWR for SSI test abjustment value PR521 change from 97.6k to 100k 26 P38 VCORE 2013/11/25 PWR current rating issue PC520 change from 0402 to 0603 27 P41 Charger_BQ24777 2013/11/26 PWR check circuit modify error PQ708A swap pin1 and pin6 28 P39 +VCCIO 2013/11/28 PWR for buyer suggest change to material PR303 chang from SD00001FX00 to SD013000080 29 P41 Charger_BQ24777 2013/11/28 PWR Vendor spec BQ24777_REGN modify to 5.4V PR715 change from 121k to 154k 30 P38 VCORE 2013/12/04 PWR DFB issue remove PL503 24 P41 Charger_BQ24777 2014/2/17 PWR peak shift issue PR729 NC 25 P41 Charger_BQ24777 2014/2/17 PWR PIN21 change from NC to input current limit mode leakage current issue PIN9 change from Voltage monitor to current monitor add PR706 10Kohm and pull high add Erp lot6 circuit 26 P41 Charger_BQ24777 2014/2/17 PWR 27 P41 Charger_BQ24777 2014/2/17 PWR 28 P33 DCIN/BATT CONN/OTP 2014/2/17 PWR Hiccup mode issue 29 P41 Charger_BQ24777 2014/2/21 PWR plug Adapter system no work issue add PR741 connect PQ709 Gate to GND C B change PD701(SCS00003800) to PD702,PD703(SCS0340L010) change PC753(100P) to PR732 (20K) 30 P38 VCORE 2014/3/4 PWR CPU change from 28W to 15W PR535 change form 210 to 200, PR537 change form 1.58k to 1.27k PR507 change from 205k to 169k, PR521 change from 100k to 97.7k 31 P41 Charger_BQ24777 2014/3/5 PWR acoustic noise add PC730,PC731,PC732 to de-pop Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A Compal Electronics, Inc Compal Secret Data Security Classification D Pc723/PC724/PC725 (0.1uF) change from de-pop to pop for SSI test abjustment value 11 B A R ev Solution D escription D C PWR-PIR Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet 43 of 47 V ersion Change L ist ( P I R L ist ) Item P age# T itle R equest O w ner D ate Page Issue D escription R ev Solution D escription 2014/3/5 PWR EMI issue Charger_BQ24777 2014/3/11 PWR Follow Houston test summary P38 VCORE 2014/3/11 PWR acoustic noise Change PC515 PC533 from VCC_PWR_SRC to B+ 35 P37 +1.35VP/0.675VSP 2014/3/14 PWR select the correct voltage to 2.5V PC214 change from SF000003000 to SF000003100 36 P33 DCIN/BATT CONN/OTP 2014/3/17 PWR hiccup mode issue 37 P34 3.3VALWP/5VALWP 2014/3/17 PWR Co-Lay 38 P41 Charger_BQ24777 2014/3/17 PWR follow 39 P41 Charger_BQ24777 2014/3/21 PWR hiccup mode issue change PR739 from 316K to 294K 40 P34 3.3VALWP/5VALWP 2014/3/24 PWR follow PR110 NC 41 P41 Charger_BQ24777 2014/5/8 PWR charger IC 42 P38 VCORE 2014/5/8 PWR power design guideline PC533 change from de-pop to pop 43 P43 Charger_BQ24777 2014/5/8 PWR BIOS Power Event Log no AC_Removed event log available PR739 change from 294k to 34k PR740 change from 49.9k to 6.49k 44 P38 VCORE 2014/5/14 PWR can't meet derating criteria PC533 change from SGA00006B00 to SGA00008R00 45 P41 Charger_BQ24777 2014/5/20 PWR charger IC PC730,PC731,PC732 change from pop to de-pop 46 All ohm to short pad 2014/5/22 PWR change footprint for ohm cost down change PR100,PR101,PR201,PR202,PR300,PR505,PR506,PR508,PR510 ,PR511,PR705,PR714,PR716,PR717,PR718,PR719,PR720,PR721,PR728,PR738 47 P34 3.3VALWP/5VALWP 2014/7/7 PWR can't power on at 0C chamber for Dino project PR110 chang to pop 32 P40 33 P41 34 PROCESSOR DECOUPLING add PC943,PC944,PC945,PC946,PC947 to de-pop solution NC PQ708A,PQ708B NC D D C add PR13 NC add PC116 PC117 NC change PR725 from 100K to 1K TI solution EC solution ripple issue PC730,PC731,PC732 change from de-pop to pop ripple issue 48 P41 Charger_BQ24777 2014/7/8 PWR buyer suggest PR748 change from SE000001380to SE000006900 49 P41 Charger_BQ24777 2014/7/8 PWR buyer suggest 50 P33 DCIN/BATT CONN/OTP 2014/7/7 PWR DFB issue PC701,PC750 change from SE00000DR00 to SE00000G880 PD3 footprint change form AZ5125-01HPR7G_SOD523-2 to RB751S40T1G_SOD523-2 51 P33 DCIN/BATT CONN/OTP 2014/7/15 PWR 52 P34 3.3VALWP/5VALWP 2014/7/16 DFB issue can't power on at 0C chamber issue EC comfirm de-pop PWR C change PD3 from SC400005Q00 to SC400008400 PR110 chang to de-pop B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/07/25 Deciphered Date 2014/07/24 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PWR-PIR Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet 44 of 47 V ersion Change L ist ( P I R L ist ) Item P age# D C B D ate Page Issue D escription Solution D escription R ev DC/DC Interface 2013/10/08 EE Add capacitor for fine tune Codec power up timing Add C5292, C5293 for U2301 X01 EE Change Fuse package for sales suggestion Change F1 From SP040003E00 to SP040003A00 X01 30 KB control 2013/10/08 23 Audio Codec ALC3234 2013/10/08 EE Add EMI solution for Ring2 & Sleeve Add RA1126, RA1127 to SM01000FG00 X01 23 Audio Codec ALC3234 2013/10/08 EE Add pull down resistor for Audio sense pin floating Add RA1128 from 100K to GND for AUD_HP_NB_SENSE X01 EE Cost down Reserve CA75 to NC X01 23 Audio Codec ALC3234 2013/10/08 23 Audio Codec ALC3234 2013/10/08 EE Correct power source for codec Change RC366 from +3VALW to +3VA, and NC RC366 X01 23 Audio Codec ALC3234 2013/10/08 EE Correct Jack sense pin funtion voltage level Delete RA1118 & RA1119 X01 27 LED/DB 2013/10/08 EE For touch pad control issue Add R2529, R2530, R2531 from 2.2K to +3VS_TP X01 22 LAN RTL8111GUS-CG 2013/10/21 EE Change LAN bead for power Regular Change L18 from SHI00008M00 to SHI0000AA00 X01 10 20 DP to CRT 2013/10/21 EE fix +3VS leakage issue Change RV161, RV162, RV215 from +5VS to +3VS_VGA, Add RV516, RV517, QV89 for DDC of CRT X01 11 20 DP to CRT 2013/10/21 EE Remove Crystal circuit for Vendor confirm Depop YV3, RV210, RV159, CV344, CV345 X01 12 21, 28 eDP/webcam/touch 2013/10/21 EE no support DCR function Delete RC61, RC79 and net DCR_EN X01 13 30 KB control 2013/10/21 EE change net name by EC request Change net name KB_BL_DET to BKLGT_DET, Change net name KB_LED_PWM to BKLT_PWM, Change net name CAPS_LED# to CAP_LED X01 14 27 LED/DB 2013/10/21 EE Fix LED blink by leakage issue Delete CZ48, UZ10 X01 15 27 LED/DB 2013/10/21 EE Fix leakage issue Change RZ24 from +3VALW to +3VS X01 16 29 KBC & GPIO MEC5085 2013/10/21 EE Change net name by EC request Change net name from VCP to I_ADP, Change net name from V_SYS to I_BATT X01 17 23 Audio Codec ALC3234 2013/10/21 EE fine tune PC Beep sound Change RA79 to 20K,and pop RA81 to 10K X01 18 23 Audio Codec ALC3234 2013/10/21 EE fix POP noise issue Add RA1129 from 100K to UA1 pin 27 X01 19 ALL ALL 2013/10/21 EE Re-name part of connector 20 ALL ALL 2013/10/21 EE Re-name part of jump JCRT1 > JCRT, JAPS1 > JAPS, JDEG1 > JDEG, JLPDE1 > JLPDE, JKB1 > JKB, JNGFF1 > JNGFF, JXDP1 > JXDP, JRTC1 > JRTC, PJPDC1 > JDCIN, PBATT1 > JBATT PJ200 > PJP200, PJ201 > PJP201, PJ203 > PJP203, PJ400 > PJP400, PJ401 > PJP401, JP12 > PJP12 JP13 > PJP13, J510 > PJP510, J511 > PJP511, J512 > PJP512, J513 > PJP513 21 23 Audio Codec ALC3234 2013/10/23 EE Update P/N for X1 code issue Change LA8, LA9 form SM010018110 to SM01000EI00 X01 22 19 HDMI 2013/10/29 EE Change Array Resistor for Broadway CPU Change RP58, RP59 from 680 to 470 ohm X01 X01 29 KBC & GPIO MEC5085 2013/10/31 EE Depop item by EC request Depop RE278 22 LAN RTL8111GUS-CG 2013/10/31 EE Change Power switch for cost down plan Change UL2 from SA00003AR00 to SA000079400, Delete CL38, Add RL41 to 100K X01 25 21 eDP/webcam/touch 2013/10/31 EE Change Power switch for cost down plan Change UX1, UX3 from SA00003AR00 to SA000079400, Delete CX9, CX52, Add RX30, RX31 to 100K X01 26 31 DC/DC interface 2013/10/31 EE Change Load switch for cost down plan Change U2301, U2304 from SA00004MM00 to SA00006FD00 X01 27 25 NGFF_WLAN 2013/10/31 EE Change Power switch for cost down plan Change UM1 from SA00005XM00 to SA000070L00, Add CM8 to 2200P X01 28 22 LAN RTL8111GUS-CG 2013/10/31 EE Change Transformer for cost down plan Change TL2 from SP050007Q00 to SP050006P00 X01 29 20 DP to CRT 2013/11/05 EE Add capacitor for reduce power ripple by vendor confirm Add CV361 to 22uF and close UV6 pin 38 X01 30 23 Audio Codec ALC3234 2013/11/05 EE Add capacitor for codec stable Add CA77 to 4.7uF_0603 and close UA1 pin36 X01 31 19,24, 26,27 Common mode Choke 2013/11/12 EE Change Common mode choke for X1 code Change L12,LX2,LI2,LX3,LX4,LX5,LI5,LX6,LX7,LI9,LI10 from SM070001S00 to SM070003Y00, Change LI1, LI3, LI4, LI6 from SM070001R00 to SM070003Q00 X01 32 27 LED/DB 2013/11/12 EE Delete MB common mode choke by EA measure Delete LI9, LI10 X01 33 24, 27 USB 2013/11/13 EE Change USB I/O power switch for Cost down Change UI2, UI3, UI4 from SA00003XM00 to SA00007AO00, Delete CI7, CI14, CI18, CI45, Change CI6, CI12, CI44 from 4.7U_0805 to 1U_0603 X01 34 13, 17 Buffer output 2013/11/13 EE change buffer output for cost down Change UC6, U2303 from SA00005U600 to SA00007KJ00 X01 35 17, 27, 30 DDR & LED & KB 2013/11/14 EE change MOSFET for cost down Change Q12, QE11, Q327 from SB00000UO00 to SB00000ST00, Change QD2 from SB501380050 to SB00000ST00 X01 2013/11/15 EE modify by EMC request Change CA38, CA40 from 100p to 680p X01 36 23 Audio Codec ALC3234 37 23 Audio Codec ALC3234 2013/11/18 EE Change EMI solution Change RA1121, RA1122, RA1123, RA1124 from ohm to SM01000NO00 X01 KBC & GPIO MEC5085 2013/11/18 EE Add ESD diode by EMC request Add DE2 for PECI_EC net X01 39 26 40 08, 29 41 20 HDD/Finger print 2013/11/19 EE Rename Location Re-name U2413 to DS1 X01 Crystal 2013/11/20 EE Crystal fine tune Change CC1 from 15P to 18P, Change CE53, CE62 from 22P to 33P X01 DP to CRT 2013/11/21 EE Add Power pin connect to power by vendor Add RV518 10K to +3VS_VGA X01 Issued Date 2013/04/10 Deciphered Date 2014/05/01 Date: A Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B Compal Electronics, Inc Compal Secret Data Security Classification C X01 23 29 D X01 24 38 A 31 T itle R equest O w ner NOTE Document Number Rev 1.0 LA-B071P Wednesday, July 30, 2014 Sheet 45 of 47 ... Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/08/01 Deciphered Date 2014/07/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,... Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/08/01 Deciphered Date 2014/07/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,... Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/08/01 Deciphered Date 2014/07/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,